snlavaiseandClaude Opus 5.5
8a87204d48
Bring-up of the Moto Edge 40 Pro (rtwo) on the SM8550 kernel: - dts: NT37705 DSI panel with DSC, Goodix GT9916P touch, ADSP/CDSP with pmic-glink (battery, UCSI), Adreno 740, WiFi (WCN7850/ath12k), physical keys, and USB-C DisplayPort (pmic-glink altmode -> PS5169 redriver -> FSA4480 -> QMP combo PHY -> mdss_dp0) following the sm8550-qrd layout. - DP link capped at HBR (link-frequencies on &mdss_dp0_out): the DP->HDMI converter of a common USB-C hub trains fine at HBR2 but its HDMI output flickers and drops HPD; HBR x2 still covers 1080p60. - new drivers: typec-mux-ps5169.c (Parade PS5169 redriver as typec switch/retimer), panel-novatek-nt37705.c. - patches: msm DP invalid LTTPR caps + no push_idle with the link down (hardware reset on unplug), msm DSI keeps the panel DSC config, ath12k regd fixes and MHI keep-awake, ICC keepalive for the MDP fetch path. - rtwo.config / config-motorola-rtwo.aarch64: options for all of the above. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DnHwDU5yL8L6qgPEN5CV5m
55 lines
1.8 KiB
Diff
55 lines
1.8 KiB
Diff
--- a/drivers/gpu/drm/msm/dp/dp_display.c
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+++ b/drivers/gpu/drm/msm/dp/dp_display.c
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@@ -251,16 +251,34 @@
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int rc, lttpr_count;
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if (drm_dp_read_lttpr_common_caps(dp->aux, dpcd, dp->link->lttpr_common_caps))
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- return 0;
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+ goto no_lttpr;
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+
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+ /*
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+ * Some sinks without LTTPR support (e.g. DP->HDMI converters) mirror
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+ * their receiver caps at 0xf0000 instead of NAKing the read. Only
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+ * trust the block if it carries a valid LTTPR structure revision and
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+ * repeater count: otherwise the caps would clamp the link to whatever
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+ * lands in the "max lane count"/"max link rate" slots, and writing
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+ * PHY_REPEATER_MODE would end up in the sink's own DPCD.
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+ */
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+ if (dp->link->lttpr_common_caps[0] < 0x14)
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+ goto no_lttpr;
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lttpr_count = drm_dp_lttpr_count(dp->link->lttpr_common_caps);
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+ if (lttpr_count < 0)
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+ goto no_lttpr;
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+
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rc = drm_dp_lttpr_init(dp->aux, lttpr_count);
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if (rc) {
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DRM_ERROR("failed to set LTTPRs transparency mode, rc=%d\n", rc);
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- return 0;
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+ goto no_lttpr;
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}
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return lttpr_count;
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+
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+no_lttpr:
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+ memset(dp->link->lttpr_common_caps, 0, sizeof(dp->link->lttpr_common_caps));
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+ return 0;
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}
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static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *dp)
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--- a/drivers/gpu/drm/msm/dp/dp_panel.c
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+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
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@@ -101,6 +101,12 @@
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msm_dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd);
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link_info = &msm_dp_panel->link_info;
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+ /*
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+ * Everything below is derived from the current sink. Start from
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+ * scratch so a rate from a previous sink (the fallback path only runs
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+ * when rate is 0) does not stick across unplug/replug.
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+ */
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+ memset(link_info, 0, sizeof(*link_info));
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link_info->revision = dpcd[DP_DPCD_REV];
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major = (link_info->revision >> 4) & 0x0f;
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minor = link_info->revision & 0x0f;
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