Import U-Boot v2026.07 (unmodified upstream source, base for rtwo patches)

2026-09-16 23:15:56 -03:00
commit 391981275c
38022 changed files with 8370285 additions and 0 deletions
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+if TARGET_SMEGW01
+
+config SYS_BOARD
+	default "smegw01"
+
+config SYS_VENDOR
+	default "storopack"
+
+config SYS_CONFIG_NAME
+	default "smegw01"
+
+config IMX_CONFIG
+	default "board/storopack/smegw01/imximage.cfg"
+
+config SYS_BOOT_LOCKED
+	bool "Lock boot process to EMMC"
+	default y
+	help
+	  Say N here if you want to boot from eMMC and SD.
+	  Say Y to boot from eMMC.
+
+endif
@@ -0,0 +1,7 @@
+SMEGW01 BOARD
+M:	Fabio Estevam <festevam@denx.de>
+S:	Maintained
+F:	board/storopack/
+F:	arch/arm/dts/imx7d-smegw01.dts
+F:	configs/smegw01_defconfig
+F:	include/configs/smegw01.h
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2016 NXP Semiconductors
+
+obj-y  := smegw01.o
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 PHYTEC America, LLC
+ *
+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+IMAGE_VERSION	2
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* DDR initialization came from Phytec */
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+/* deassert presetn */
+DATA 4 0x30391000 0x00000002
+
+/* DDR Controller Regs */
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04480000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x090e110a
+DATA 4 0x307a0104 0x0007020e
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020304
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0200 0x0000001f
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a020c 0x00000000
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+
+/* deassert presetn */
+DATA 4 0x30391000 0x00000000
+
+/* PHY Controller Regs */
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000d6e
+/* write leveling values for each byte lane */
+DATA 4 0x3079006c 0x06090108
+/* write leveling resync cycle */
+DATA 4 0x30790078 0x00000001
+DATA 4 0x30790078 0x00000000
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+DATA 4 0x30790018 0x0000000f
+
+/* start manual ZQ */
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+DATA 4 0x307900c0 0x0e447304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+/* end manual ZQ */
+DATA 4 0x307900c0 0x0e407304
+
+/* final init sequence */
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0+
+// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/hab.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/io.h>
+#include <env.h>
+#include <env_internal.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \
+			PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+};
+
+static int setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
+			(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+	int ret;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			(IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
+			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
+
+	ret = set_clk_enet(ENET_125MHZ);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+	setup_fec();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int board_late_init(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	unsigned char eth1addr[6];
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	/*
+	 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
+	 * since we use PMIC_PWRON to reset the board.
+	 */
+	clrsetbits_le16(&wdog->wcr, 0, 0x10);
+
+	/* Get the second MAC address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_env_set_enetaddr("eth1addr", eth1addr);
+
+	return 0;
+}
+
+uint mmc_get_env_part(struct mmc *mmc)
+{
+	uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+
+	if (part == EMMC_BOOT_PART_USER)
+		part = EMMC_HWPART_DEFAULT;
+	return part;
+}
+
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define SETUP_BOOT_MENU setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd
+#else
+#define SETUP_BOOT_MENU setup_boot_menu= \
+			if test "${mmcdev}" = 1; then \
+				setenv emmc_priority 0; \
+				setenv sd_priority 1; \
+			else setenv emmc_priority 1; \
+				setenv sd_priority 0; \
+			fi; \
+			setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \
+			setenv bootmenu_${sd_priority} SD=run boot_sd;
+#endif
+boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;
+boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;
+bootcmd=
+	if test "${bootcount}" -gt "${bootlimit}"; then
+		run altbootcmd;
+	else
+		if test "${ustate}" = 1; then
+			setenv upgrade_available 1;
+			saveenv;
+		fi;
+		run mmcboot;
+	fi;
+bootdelay=2
+bootlimit=3
+bootm_size=0x10000000
+commit_mmc=
+	if test "${ustate}" = 1 -a "${mmcpart}" != "${mmcpart_committed}"; then
+		setenv mmcpart_committed ${mmcpart};
+		saveenv;
+	fi;
+console=ttymxc0
+loadbootpart=mmc partconf 1 boot_part
+loadimage=load mmc ${mmcdev}:${gpt_partition_entry}
+loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}
+mmcargs=
+	setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}
+mmcboot=
+	echo Booting...;
+	echo mmcdev: ${mmcdev};
+	run commit_mmc;
+	echo mmcpart: ${mmcpart_committed};
+	run loadpart;
+	echo gptpart: ${gpt_partition_entry};
+	run loadbootpart;
+	if run loadimage; then
+		;
+	else
+		run altbootcmd;
+	fi;
+#ifdef CONFIG_SYS_BOOT_LOCKED
+	hab_auth_img_or_fail ${fileaddr} ${filesize};
+#else
+	hab_auth_img ${fileaddr} ${filesize};
+#endif
+	run mmcargs;
+	if bootm; then
+		;
+	else
+		run altbootcmd;
+	fi;
+mmcdev=1
+mmcpart=1
+mmcpart_committed=1
+persist_mmcdev=
+	if test "${mmcdev}" != "${mmcdev_wanted}"; then
+		setenv mmcdev "${mmcdev_wanted}";
+		saveenv;
+	fi;
+setup_boot_menu=
+	if test "${mmcdev}" = 1; then
+		setenv emmc_priority 0;
+		setenv sd_priority 1;
+	else
+		setenv emmc_priority 1;
+		setenv sd_priority 0;
+	fi;
+	setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;
+	setenv bootmenu_${sd_priority} SD=run boot_sd;
+SETUP_BOOT_MENU