snlavaise/uboot-rtwo
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rtwo: replace 7-segment debug digits with a boot progress bar

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The bring-up instrumentation drew two big 7-segment digits per code zone
from hot paths (board.c, serial_msm_geni.c, clk-uclass.c, clock-qcom.c),
firing dozens of times per second and slowing the boot noticeably. Drop
it and draw a 0-100% progress bar instead: rtwo_boot_progress_step() once
per initcall entry, rtwo_boot_progress_done() at the end of the boot.

The kalama-gcc-v2 GCC compatible fix from the previous commit stays.

This is the tree built with ~/pmos/uboot-chainload/build-uboot.sh
(patches/0001-rtwo-fixes-and-boot-progress-bar.patch) that produces the
u-boot-nodtb.bin currently running on the phone.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01DnHwDU5yL8L6qgPEN5CV5m
This commit is contained in:
snlavaise
2026-09-26 20:03:48 -03:00
co-authored by Claude Opus 5.5
parent 01a9184178
commit 41802fcbd9
6 changed files with 85 additions and 129 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/clk/clk-uclass.c
+2 -11
View File
@@ -657,21 +657,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
return 0;
}
void rtwo_debug_blink_zone(unsigned int zone);
int clk_enable(struct clk *clk)
{
const struct clk_ops *ops;
struct clk *clkp = NULL;
int ret;
rtwo_debug_blink_zone(23); /* CLKEN-1: entrada a clk_enable */
debug("%s(clk=%p name=%s)\n", __func__, clk, clk ? clk->dev->name : "NULL");
if (!clk_valid(clk)) {
rtwo_debug_blink_zone(24); /* CLKEN-2a: clk invalido/NULL, return temprano */
if (!clk_valid(clk))
return 0;
}
rtwo_debug_blink_zone(25); /* CLKEN-2b: clk valido, seguimos */
ops = clk_dev_ops(clk->dev);
if (CONFIG_IS_ENABLED(CLK_CCF)) {
@@ -705,10 +699,7 @@ int clk_enable(struct clk *clk)
} else {
if (!ops->enable)
return -ENOSYS;
rtwo_debug_blink_zone(26); /* CLKEN-3: justo antes de ops->enable(clk) */
ret = ops->enable(clk);
rtwo_debug_blink_zone(27); /* CLKEN-4: ops->enable(clk) retorno */
return ret;
return ops->enable(clk);
}
return 0;
drivers/clk/qcom/clock-qcom.c
+2 -18
View File
@@ -28,8 +28,6 @@
#include "clock-qcom.h"
void rtwo_debug_blink_zone(unsigned int zone);
/* CBCR register fields */
#define CBCR_BRANCH_ENABLE_BIT BIT(0)
#define CBCR_BRANCH_OFF_BIT BIT(31)
@@ -78,21 +76,17 @@ void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk)
int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
rtwo_debug_blink_zone(28); /* GATE-1: entrada a qcom_gate_clk_en */
if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
log_err("gcc@%#08llx: unknown clock ID %lu!\n",
priv->base, id);
return -ENOENT;
}
rtwo_debug_blink_zone(29); /* GATE-2: id valido, antes de setbits_le32 */
setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val);
rtwo_debug_blink_zone(30); /* GATE-3: post setbits_le32 (el registro ya se escribio) */
if (priv->data->clks[id].cbcr_reg) {
unsigned int count;
u32 val;
rtwo_debug_blink_zone(31); /* GATE-4: hay cbcr_reg, entrando al poll acotado */
for (count = 0; count < 200; count++) {
val = readl(priv->base + priv->data->clks[id].cbcr_reg);
val &= BRANCH_CHECK_MASK;
@@ -100,14 +94,10 @@ int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
break;
udelay(1);
}
rtwo_debug_blink_zone(33); /* GATE-5: poll terminado (por bit ok o por timeout) */
if (WARN(count == 200, "WARNING: Clock @ %#lx [%#010x] stuck at off\n",
priv->data->clks[id].cbcr_reg, val))
return -EBUSY;
} else {
rtwo_debug_blink_zone(32); /* GATE-4b: no hay cbcr_reg, no se espera nada */
}
rtwo_debug_blink_zone(34); /* GATE-6: fin de qcom_gate_clk_en, return 0 */
return 0;
}
@@ -266,14 +256,8 @@ static int msm_clk_enable(struct clk *clk)
{
struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(clk->dev);
rtwo_debug_blink_zone(35); /* MSMCLK-1: entrada a msm_clk_enable */
if (data->enable) {
int ret;
rtwo_debug_blink_zone(36); /* MSMCLK-2: antes de data->enable(clk) */
ret = data->enable(clk);
rtwo_debug_blink_zone(37); /* MSMCLK-3: data->enable(clk) retorno */
return ret;
}
if (data->enable)
return data->enable(clk);
return 0;
}
drivers/clk/qcom/clock-sm8550.c
-5
View File
@@ -198,14 +198,10 @@ static const struct gate_clk sm8550_clks[] = {
GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x39068, BIT(0)),
};
void rtwo_debug_blink_zone(unsigned int zone);
static int sm8550_enable(struct clk *clk)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
rtwo_debug_blink_zone(38); /* SM8550EN-1: entrada a sm8550_enable, id=%clk->id (sin printf aqui) */
switch (clk->id) {
case GCC_AGGRE_USB3_PRIM_AXI_CLK:
qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
@@ -224,7 +220,6 @@ static int sm8550_enable(struct clk *clk)
break;
}
rtwo_debug_blink_zone(39); /* SM8550EN-2: post switch, antes de qcom_gate_clk_en final */
return qcom_gate_clk_en(priv, clk->id);
}
drivers/serial/serial_msm_geni.c
-21
View File
@@ -19,8 +19,6 @@
#include <soc/qcom/qup-fw-load.h>
#include <soc/qcom/geni-se.h>
void rtwo_debug_blink_zone(unsigned int zone);
#define UART_OVERSAMPLING 32
#define STALE_TIMEOUT 160
@@ -211,15 +209,12 @@ static int msm_serial_setbrg(struct udevice *dev, int baud)
pr_err("%s: Couldn't get clock division rate\n", __func__);
return -EINVAL;
}
rtwo_debug_blink_zone(10); /* SETBRG-1: pre clk_set_rate */
ret = clk_set_rate(priv->se, clk_rate);
rtwo_debug_blink_zone(11); /* SETBRG-2: post clk_set_rate */
if (ret < 0) {
pr_err("%s: Couldn't set clock rate: %d\n", __func__, ret);
return 0;
}
geni_serial_baud(priv->base, clk_div, baud);
rtwo_debug_blink_zone(12); /* SETBRG-3: post geni_serial_baud */
return 0;
}
@@ -522,8 +517,6 @@ static int msm_serial_probe(struct udevice *dev)
u32 proto;
struct clk *clk;
rtwo_debug_blink_zone(13); /* PROBE-1: entrada */
clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(clk)) {
/*
@@ -539,13 +532,9 @@ static int msm_serial_probe(struct udevice *dev)
priv->se = clk;
}
rtwo_debug_blink_zone(14); /* PROBE-2: post devm_clk_get_optional */
/* Try enable clock */
clk_enable(clk);
rtwo_debug_blink_zone(15); /* PROBE-3: post clk_enable */
/* Check if firmware loading is needed (BT UART) */
proto = readl(priv->base + GENI_FW_REVISION_RO);
proto &= FW_REV_PROTOCOL_MSK;
@@ -558,8 +547,6 @@ static int msm_serial_probe(struct udevice *dev)
proto >>= FW_REV_PROTOCOL_SHFT;
}
rtwo_debug_blink_zone(16); /* PROBE-4: post firmware check/load */
if (proto != GENI_SE_UART) {
dev_err(dev, "Invalid proto %d\n", proto);
clk_disable(clk);
@@ -570,26 +557,18 @@ static int msm_serial_probe(struct udevice *dev)
if (ofnode_device_is_compatible(dev_ofnode(dev), "qcom,geni-uart"))
return -ENOENT;
rtwo_debug_blink_zone(17); /* PROBE-5: es geni-debug-uart, seguimos */
ret = geni_set_oversampling(dev);
if (ret < 0)
return ret;
rtwo_debug_blink_zone(18); /* PROBE-6: post geni_set_oversampling */
/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
return 0;
geni_serial_init(dev);
rtwo_debug_blink_zone(19); /* PROBE-7: post geni_serial_init */
msm_geni_serial_setup_rx(dev);
rtwo_debug_blink_zone(20); /* PROBE-8: post msm_geni_serial_setup_rx */
qcom_geni_serial_start_rx(dev);
rtwo_debug_blink_zone(21); /* PROBE-9: post qcom_geni_serial_start_rx */
qcom_geni_serial_start_tx(priv->base);
rtwo_debug_blink_zone(22); /* PROBE-10: post qcom_geni_serial_start_tx, fin de probe */
return 0;
}