50 lines
1.5 KiB
C
50 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Mocha SPL stage configuration
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*
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* (C) Copyright 2024
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* Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <linux/delay.h>
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#define TPS65913_I2C_ADDR (0x58 << 1)
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#define TPS65913_SMPS12_CTRL 0x20
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#define TPS65913_SMPS12_VOLTAGE 0x23
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#define TPS65913_SMPS45_CTRL 0x28
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#define TPS65913_SMPS45_VOLTAGE 0x2B
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#define TPS65913_SMPS7_CTRL 0x30
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#define TPS65913_SMPS7_VOLTAGE 0x33
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#define TPS65913_SMPS12_CTRL_DATA (0x5100 | TPS65913_SMPS12_CTRL)
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#define TPS65913_SMPS12_VOLTAGE_DATA (0x3800 | TPS65913_SMPS12_VOLTAGE)
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#define TPS65913_SMPS45_CTRL_DATA (0x5100 | TPS65913_SMPS45_CTRL)
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#define TPS65913_SMPS45_VOLTAGE_DATA (0x3800 | TPS65913_SMPS45_VOLTAGE)
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#define TPS65913_SMPS7_CTRL_DATA (0x5100 | TPS65913_SMPS7_CTRL)
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#define TPS65913_SMPS7_VOLTAGE_DATA (0x4700 | TPS65913_SMPS7_VOLTAGE)
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void pmic_enable_cpu_vdd(void)
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{
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/* Set CORE VDD to 1.150V. */
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tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS7_VOLTAGE_DATA);
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udelay(1000);
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tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS7_CTRL_DATA);
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udelay(1000);
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/* Set CPU VDD to 1.0V. */
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tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_VOLTAGE_DATA);
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udelay(1000);
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tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS12_CTRL_DATA);
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udelay(10 * 1000);
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/* Set GPU VDD to 1.0V. */
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tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_VOLTAGE_DATA);
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udelay(1000);
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tegra_i2c_ll_write(TPS65913_I2C_ADDR, TPS65913_SMPS45_CTRL_DATA);
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udelay(10 * 1000);
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}
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