581 lines
16 KiB
C
581 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2025, Linaro Ltd.
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*/
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#define pr_fmt(fmt) "GENI-SE: " fmt
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#include <blk.h>
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#include <part.h>
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#include <dm/device.h>
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#include <dm/read.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <elf.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <misc.h>
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#include <linux/printk.h>
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#include <soc/qcom/geni-se.h>
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#include <soc/qcom/qup-fw-load.h>
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#include <dm/device_compat.h>
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struct qup_se_rsc {
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phys_addr_t base;
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phys_addr_t wrapper_base;
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struct udevice *dev;
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enum geni_se_xfer_mode mode;
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enum geni_se_protocol_type protocol;
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};
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struct geni_se_plat {
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bool need_firmware_load;
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};
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/**
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* geni_enable_interrupts() Enable interrupts.
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* @rsc: Pointer to a structure representing SE-related resources.
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*
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* Enable the required interrupts during the firmware load process.
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*
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* Return: None.
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*/
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static void geni_enable_interrupts(struct qup_se_rsc *rsc)
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{
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u32 reg_value;
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/* Enable required interrupts. */
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writel_relaxed(M_COMMON_GENI_M_IRQ_EN, rsc->base + GENI_M_IRQ_ENABLE);
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reg_value = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN |
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S_CMD_CANCEL_EN | S_CMD_ABORT_EN |
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S_GP_IRQ_0_EN | S_GP_IRQ_1_EN |
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S_GP_IRQ_2_EN | S_GP_IRQ_3_EN |
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S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN;
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writel_relaxed(reg_value, rsc->base + GENI_S_IRQ_ENABLE);
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/* DMA mode configuration. */
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reg_value = DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK |
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DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK |
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DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK;
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writel_relaxed(reg_value, rsc->base + DMA_TX_IRQ_EN_SET);
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reg_value = DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK |
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DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK |
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DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK |
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DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK;
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writel_relaxed(reg_value, rsc->base + DMA_RX_IRQ_EN_SET);
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}
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/**
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* geni_flash_fw_revision() - Flash the firmware revision.
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* @rsc: Pointer to a structure representing SE-related resources.
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* @hdr: Pointer to the ELF header of the Serial Engine.
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*
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* Flash the firmware revision and protocol into the respective register.
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*
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* Return: None.
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*/
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static void geni_flash_fw_revision(struct qup_se_rsc *rsc, struct elf_se_hdr *hdr)
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{
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u32 reg_value;
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/* Flash firmware revision register. */
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reg_value = (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) |
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(hdr->fw_version & 0xFF << FW_REV_VERSION_SHFT);
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writel_relaxed(reg_value, rsc->base + SE_GENI_FW_REVISION);
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reg_value = (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) |
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(hdr->fw_version & 0xFF << FW_REV_VERSION_SHFT);
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writel_relaxed(reg_value, rsc->base + SE_S_FW_REVISION);
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}
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/**
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* geni_configure_xfer_mode() - Set the transfer mode.
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* @rsc: Pointer to a structure representing SE-related resources.
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*
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* Set the transfer mode to either FIFO or DMA according to the mode specified by the protocol
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* driver.
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*
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* Return: 0 if successful, otherwise return an error value.
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*/
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static int geni_configure_xfer_mode(struct qup_se_rsc *rsc)
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{
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/* Configure SE FIFO, DMA or GSI mode. */
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switch (rsc->mode) {
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case GENI_GPI_DMA:
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geni_setbits32(rsc->base + QUPV3_SE_GENI_DMA_MODE_EN,
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GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK);
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writel_relaxed(0x0, rsc->base + SE_IRQ_EN);
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writel_relaxed(SE_GSI_EVENT_EN_BMSK, rsc->base + SE_GSI_EVENT_EN);
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break;
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case GENI_SE_FIFO:
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geni_clrbits32(rsc->base + QUPV3_SE_GENI_DMA_MODE_EN,
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GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK);
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writel_relaxed(SE_IRQ_EN_RMSK, rsc->base + SE_IRQ_EN);
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writel_relaxed(0x0, rsc->base + SE_GSI_EVENT_EN);
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break;
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case GENI_SE_DMA:
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geni_setbits32(rsc->base + QUPV3_SE_GENI_DMA_MODE_EN,
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GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK);
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writel_relaxed(SE_IRQ_EN_RMSK, rsc->base + SE_IRQ_EN);
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writel_relaxed(0x0, rsc->base + SE_GSI_EVENT_EN);
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break;
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default:
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dev_err(rsc->dev, "invalid se mode: %d\n", rsc->mode);
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return -EINVAL;
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}
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return 0;
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}
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/**
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* geni_config_common_control() - Configure common CGC and disable high priority interrupt.
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* @rsc: Pointer to a structure representing SE-related resources.
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*
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* Configure the common CGC and disable high priority interrupts until the current low priority
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* interrupts are handled.
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*
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* Return: None.
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*/
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static void geni_config_common_control(struct qup_se_rsc *rsc)
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{
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/*
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* Disable high priority interrupt until current low priority interrupts are handled.
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*/
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geni_setbits32(rsc->wrapper_base + QUPV3_COMMON_CFG,
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FAST_SWITCH_TO_HIGH_DISABLE_BMASK);
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/*
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* Set AHB_M_CLK_CGC_ON to indicate hardware controls se-wrapper cgc clock.
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*/
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geni_setbits32(rsc->wrapper_base + QUPV3_SE_AHB_M_CFG,
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AHB_M_CLK_CGC_ON_BMASK);
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/* Let hardware to control common cgc. */
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geni_setbits32(rsc->wrapper_base + QUPV3_COMMON_CGC_CTRL,
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COMMON_CSR_SLV_CLK_CGC_ON_BMASK);
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}
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static int load_se_firmware(struct qup_se_rsc *rsc, struct elf_se_hdr *hdr)
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{
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const u32 *fw_val_arr, *cfg_val_arr;
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const u8 *cfg_idx_arr;
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u32 i, reg_value, mask, ramn_cnt;
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int ret;
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fw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);
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cfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;
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cfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);
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geni_config_common_control(rsc);
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/* Allows to drive corresponding data according to hardware value. */
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writel_relaxed(0x0, rsc->base + GENI_OUTPUT_CTRL);
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/* Set SCLK and HCLK to program RAM */
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geni_setbits32(rsc->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
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GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
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writel_relaxed(0x0, rsc->base + SE_GENI_CLK_CTRL);
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geni_clrbits32(rsc->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
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GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
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/* Enable required clocks for DMA CSR, TX and RX. */
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reg_value = DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK |
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DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK |
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DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK |
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DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK;
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geni_setbits32(rsc->base + DMA_GENERAL_CFG, reg_value);
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/* Let hardware control CGC by default. */
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writel_relaxed(DEFAULT_CGC_EN, rsc->base + GENI_CGC_CTRL);
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/* Set version of the configuration register part of firmware. */
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writel_relaxed(hdr->cfg_version, rsc->base + GENI_INIT_CFG_REVISION);
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writel_relaxed(hdr->cfg_version, rsc->base + GENI_S_INIT_CFG_REVISION);
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/* Configure GENI primitive table. */
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for (i = 0; i < hdr->cfg_size_in_items; i++)
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writel_relaxed(cfg_val_arr[i],
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rsc->base + GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32)));
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/* Configure condition for assertion of RX_RFR_WATERMARK condition. */
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reg_value = readl_relaxed(rsc->base + QUPV3_SE_HW_PARAM_1);
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mask = (reg_value >> RX_FIFO_WIDTH_BIT) & RX_FIFO_WIDTH_MASK;
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writel_relaxed(mask - 2, rsc->base + GENI_RX_RFR_WATERMARK_REG);
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/* Let hardware control CGC */
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geni_setbits32(rsc->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK);
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ret = geni_configure_xfer_mode(rsc);
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if (ret) {
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dev_err(rsc->dev, "failed to configure xfer mode: %d\n", ret);
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return ret;
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}
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geni_enable_interrupts(rsc);
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geni_flash_fw_revision(rsc, hdr);
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ramn_cnt = hdr->fw_size_in_items;
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if (hdr->fw_size_in_items % 2 != 0)
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ramn_cnt++;
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if (ramn_cnt >= MAX_GENI_CFG_RAMn_CNT) {
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dev_err(rsc->dev, "firmware size is too large\n");
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return -EINVAL;
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}
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/* Program RAM address space. */
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for (i = 0; i < hdr->fw_size_in_items; i++)
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writel_relaxed(fw_val_arr[i], rsc->base + SE_GENI_CFG_RAMN + i * sizeof(u32));
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/* Put default values on GENI's output pads. */
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writel_relaxed(0x1, rsc->base + GENI_FORCE_DEFAULT_REG);
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/* High to low SCLK and HCLK to finish RAM. */
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geni_setbits32(rsc->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
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GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
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geni_setbits32(rsc->base + SE_GENI_CLK_CTRL, GENI_CLK_CTRL_SER_CLK_SEL_BMSK);
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geni_clrbits32(rsc->base + GENI_CGC_CTRL, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
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GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
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/* Serial engine DMA interface is enabled. */
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geni_setbits32(rsc->base + SE_DMA_IF_EN, DMA_IF_EN_DMA_IF_EN_BMSK);
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/* Enable or disable FIFO interface of the serial engine. */
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if (rsc->mode == GENI_SE_FIFO)
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geni_clrbits32(rsc->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
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else
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geni_setbits32(rsc->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE);
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return 0;
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}
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/**
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* elf_phdr_valid() - Validate an ELF header.
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* @phdr: Pointer to the ELF header.
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*
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* Validate the ELF header by comparing the fields stored in p_flags and the payload type.
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*
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* Return: true if the validation is successful, false otherwise.
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*/
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static bool elf_phdr_valid(const Elf32_Phdr *phdr)
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{
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if (phdr->p_type != PT_LOAD || !phdr->p_memsz)
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return false;
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if (MI_PBT_PAGE_MODE_VALUE(phdr->p_flags) == MI_PBT_NON_PAGED_SEGMENT &&
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MI_PBT_SEGMENT_TYPE_VALUE(phdr->p_flags) != MI_PBT_HASH_SEGMENT &&
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MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) != MI_PBT_NOTUSED_SEGMENT &&
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MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) != MI_PBT_SHARED_SEGMENT)
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return true;
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return false;
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}
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/**
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* valid_seg_size() - Validate the segment size.
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* @pelfseg: Pointer to the ELF header.
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* @p_filesz: Pointer to the file size.
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*
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* Validate the ELF segment size by comparing the file size.
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*
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* Return: true if the segment is valid, false if the segment is invalid.
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*/
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static bool valid_seg_size(struct elf_se_hdr *pelfseg, Elf32_Word p_filesz)
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{
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if (p_filesz >= pelfseg->fw_offset + pelfseg->fw_size_in_items * sizeof(u32) &&
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p_filesz >= pelfseg->cfg_idx_offset + pelfseg->cfg_size_in_items * sizeof(u8) &&
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p_filesz >= pelfseg->cfg_val_offset + pelfseg->cfg_size_in_items * sizeof(u32))
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return true;
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return false;
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}
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/**
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* read_elf() - Read an ELF file.
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* @rsc: Pointer to the SE resources structure.
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* @fw: Pointer to the firmware buffer.
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* @pelfseg: Pointer to the SE-specific ELF header.
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* @phdr: Pointer to one of the valid headers from the list in the firmware buffer.
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*
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* Read the ELF file and output a pointer to the header data, which contains the firmware data and
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* any other details.
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*
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* Return: 0 if successful, otherwise return an error value.
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*/
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static int read_elf(struct qup_se_rsc *rsc, const void *fw,
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struct elf_se_hdr **pelfseg)
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{
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Elf32_Phdr *phdr;
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const Elf32_Ehdr *ehdr = (const Elf32_Ehdr *)fw;
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Elf32_Phdr *phdrs = (Elf32_Phdr *)(ehdr + 1);
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const u8 *addr;
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int i;
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ehdr = (Elf32_Ehdr *)fw;
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if (ehdr->e_phnum < 2)
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return -EINVAL;
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for (i = 0; i < ehdr->e_phnum; i++) {
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phdr = &phdrs[i];
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if (!elf_phdr_valid(phdr))
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continue;
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if (phdr->p_filesz >= sizeof(struct elf_se_hdr)) {
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addr = fw + phdr->p_offset;
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*pelfseg = (struct elf_se_hdr *)addr;
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if ((*pelfseg)->magic == MAGIC_NUM_SE &&
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(*pelfseg)->version == 1 &&
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valid_seg_size(*pelfseg, phdr->p_filesz) &&
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(*pelfseg)->serial_protocol == rsc->protocol &&
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(*pelfseg)->serial_protocol != GENI_SE_NONE)
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return 0;
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}
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}
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return -EINVAL;
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}
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int qcom_geni_load_firmware(phys_addr_t qup_base,
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struct udevice *dev)
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{
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struct qup_se_rsc rsc;
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struct elf_se_hdr *hdr;
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int ret;
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void *fw;
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rsc.dev = dev;
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rsc.base = qup_base;
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rsc.wrapper_base = dev_read_addr(dev->parent);
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/* FIXME: GSI DMA mode if device has property qcom,gsi-dma-allowed */
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rsc.mode = GENI_SE_FIFO;
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switch (device_get_uclass_id(dev)) {
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case UCLASS_I2C:
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rsc.protocol = GENI_SE_I2C;
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break;
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case UCLASS_SPI:
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rsc.protocol = GENI_SE_SPI;
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break;
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case UCLASS_SERIAL:
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rsc.protocol = GENI_SE_UART;
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break;
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default:
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return -EINVAL;
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}
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/* The firmware blob is the private data of the GENI wrapper (parent) */
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fw = dev_get_priv(dev->parent);
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ret = read_elf(&rsc, fw, &hdr);
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if (ret) {
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dev_err(dev, "Failed to read ELF: %d\n", ret);
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return ret;
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}
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dev_info(dev, "Loading QUP firmware...\n");
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return load_se_firmware(&rsc, hdr);
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}
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/*
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* We need to determine if firmware loading is necessary. Best way to do that is to check the FW
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* revision of each QUP and see if it has already been loaded.
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*/
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static int geni_se_of_to_plat(struct udevice *dev)
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{
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ofnode child;
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struct resource res;
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u32 proto;
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struct geni_se_plat *plat = dev_get_plat(dev);
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plat->need_firmware_load = false;
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dev_for_each_subnode(child, dev) {
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if (!ofnode_is_enabled(child))
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continue;
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if (ofnode_read_resource(child, 0, &res))
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continue;
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proto = readl(res.start + GENI_FW_REVISION_RO);
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proto &= FW_REV_PROTOCOL_MSK;
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proto >>= FW_REV_PROTOCOL_SHFT;
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if (proto == GENI_SE_INVALID_PROTO)
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plat->need_firmware_load = true;
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}
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return 0;
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}
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#define QUPFW_PART_TYPE_GUID "21d1219f-2ed1-4ab4-930a-41a16ae75f7f"
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static int find_qupfw_part(struct udevice **blk_dev, struct disk_partition *part_info)
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{
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struct blk_desc *desc;
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int ret, partnum;
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uclass_foreach_dev_probe(UCLASS_BLK, *blk_dev) {
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if (device_get_uclass_id(*blk_dev) != UCLASS_BLK)
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continue;
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desc = dev_get_uclass_plat(*blk_dev);
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if (!desc || desc->part_type == PART_TYPE_UNKNOWN)
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continue;
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for (partnum = 1;; partnum++) {
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ret = part_get_info(desc, partnum, part_info);
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if (ret)
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break;
|
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if (!strcmp(part_info->type_guid, QUPFW_PART_TYPE_GUID))
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
static int probe_children_load_firmware(struct udevice *dev)
|
|
{
|
|
struct geni_se_plat *plat;
|
|
ofnode child;
|
|
struct udevice *child_dev;
|
|
struct resource res;
|
|
u32 proto;
|
|
int ret;
|
|
|
|
plat = dev_get_plat(dev);
|
|
|
|
dev_for_each_subnode(child, dev) {
|
|
if (!ofnode_is_enabled(child))
|
|
continue;
|
|
|
|
if (ofnode_read_resource(child, 0, &res))
|
|
continue;
|
|
|
|
proto = readl(res.start + GENI_FW_REVISION_RO);
|
|
proto &= FW_REV_PROTOCOL_MSK;
|
|
proto >>= FW_REV_PROTOCOL_SHFT;
|
|
|
|
if (proto != GENI_SE_INVALID_PROTO)
|
|
continue;
|
|
|
|
ret = 0;
|
|
/* Find the device for this ofnode, or bind it */
|
|
if (device_find_global_by_ofnode(child, &child_dev))
|
|
ret = lists_bind_fdt(dev, child, &child_dev, NULL, false);
|
|
if (ret) {
|
|
/* Skip nodes that don't have drivers */
|
|
debug("Failed to probe child %s: %d\n", ofnode_get_name(child), ret);
|
|
continue;
|
|
}
|
|
debug("Probing child %s for fw loading\n", child_dev->name);
|
|
device_probe(child_dev);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#define MAX_FW_BUF_SIZE (128 * 1024)
|
|
|
|
/*
|
|
* Load firmware for QCOM GENI peripherals from the dedicated partition on storage and bind/probe
|
|
* all the peripheral devices that need firmware to be loaded.
|
|
*/
|
|
static int qcom_geni_fw_initialise(void)
|
|
{
|
|
debug("Loading firmware for QCOM GENI SE\n");
|
|
struct udevice *geni_wrapper, *blk_dev;
|
|
struct disk_partition part_info;
|
|
int ret;
|
|
void *fw_buf;
|
|
size_t fw_size = MAX_FW_BUF_SIZE;
|
|
struct geni_se_plat *plat;
|
|
|
|
/* Find the first GENI SE wrapper that needs fw loading */
|
|
for (uclass_first_device(UCLASS_MISC, &geni_wrapper);
|
|
geni_wrapper;
|
|
uclass_next_device(&geni_wrapper)) {
|
|
if (device_get_uclass_id(geni_wrapper) == UCLASS_MISC &&
|
|
!strcmp(geni_wrapper->driver->name, "geni-se-qup")) {
|
|
plat = dev_get_plat(geni_wrapper);
|
|
if (plat->need_firmware_load)
|
|
break;
|
|
}
|
|
}
|
|
if (!geni_wrapper) {
|
|
pr_err("GENI SE wrapper not found\n");
|
|
return 0;
|
|
}
|
|
|
|
ret = find_qupfw_part(&blk_dev, &part_info);
|
|
if (ret) {
|
|
pr_err("QUP firmware partition not found\n");
|
|
return 0;
|
|
}
|
|
|
|
if (part_info.size * part_info.blksz > MAX_FW_BUF_SIZE) {
|
|
pr_err("Firmware partition too large\n");
|
|
return -EINVAL;
|
|
}
|
|
fw_size = part_info.size * part_info.blksz;
|
|
|
|
fw_buf = malloc(fw_size);
|
|
if (!fw_buf) {
|
|
pr_err("Failed to allocate buffer for firmware\n");
|
|
return -ENOMEM;
|
|
}
|
|
memset(fw_buf, 0, fw_size);
|
|
|
|
ret = blk_read(blk_dev, part_info.start, part_info.size, fw_buf);
|
|
if (ret < 0) {
|
|
pr_err("Failed to read firmware from partition\n");
|
|
free(fw_buf);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* OK! Firmware is loaded, now bind and probe remaining children. They will attempt to load
|
|
* firmware during probe. Do this for each GENI SE wrapper that needs firmware loading.
|
|
*/
|
|
for (; geni_wrapper;
|
|
uclass_next_device(&geni_wrapper)) {
|
|
if (device_get_uclass_id(geni_wrapper) == UCLASS_MISC &&
|
|
!strcmp(geni_wrapper->driver->name, "geni-se-qup")) {
|
|
plat = dev_get_plat(geni_wrapper);
|
|
if (plat->need_firmware_load) {
|
|
dev_set_priv(geni_wrapper, fw_buf);
|
|
probe_children_load_firmware(geni_wrapper);
|
|
}
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qcom_geni_fw_initialise);
|
|
|
|
static const struct udevice_id geni_ids[] = {
|
|
{ .compatible = "qcom,geni-se-qup" },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(geni_se_qup) = {
|
|
.name = "geni-se-qup",
|
|
.id = UCLASS_MISC,
|
|
.of_match = geni_ids,
|
|
.of_to_plat = geni_se_of_to_plat,
|
|
.plat_auto = sizeof(struct geni_se_plat),
|
|
.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
|
|
};
|