22 lines
506 B
C
22 lines
506 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Config file for BR Zynq board
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*
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* Copyright (C) 2024
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* B&R Industrial Automation GmbH - http://www.br-automation.com/
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*/
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#ifndef __CONFIG_BRZYNQ_H__
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#define __CONFIG_BRZYNQ_H__
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/* Increase PHY_ANEG_TIMEOUT since the FPGA needs some setup time */
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#if IS_ENABLED(CONFIG_SPL_FPGA)
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#define PHY_ANEG_TIMEOUT 8000
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#endif
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/* Use top mapped SRAM */
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#define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000
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#define CFG_SYS_INIT_RAM_SIZE 0x2000
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#endif /* __CONFIG_BRZYNQ_H__ */
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