114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CFG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
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#define CFG_SYS_INIT_RAM_SIZE OCRAM_SIZE
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/*
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* DDR: 800 MHz ( 1600 MT/s data rate )
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*/
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#define DDR_SDRAM_CFG 0x470c0008
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#define DDR_CS0_BNDS 0x008000bf
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#define DDR_CS0_CONFIG 0x80014302
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#define DDR_TIMING_CFG_0 0x50550004
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#define DDR_TIMING_CFG_1 0xbcb38c56
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#define DDR_TIMING_CFG_2 0x0040d120
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#define DDR_TIMING_CFG_3 0x010e1000
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#define DDR_TIMING_CFG_4 0x00000001
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#define DDR_TIMING_CFG_5 0x03401400
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#define DDR_SDRAM_CFG_2 0x00401010
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#define DDR_SDRAM_MODE 0x00061c60
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#define DDR_SDRAM_MODE_2 0x00180000
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#define DDR_SDRAM_INTERVAL 0x18600618
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#define DDR_DDR_WRLVL_CNTL 0x8655f605
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#define DDR_DDR_WRLVL_CNTL_2 0x05060607
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#define DDR_DDR_WRLVL_CNTL_3 0x05050505
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#define DDR_DDR_CDR1 0x80040000
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#define DDR_DDR_CDR2 0x00000001
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#define DDR_SDRAM_CLK_CNTL 0x02000000
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#define DDR_DDR_ZQ_CNTL 0x89080600
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#define DDR_CS0_CONFIG_2 0
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#define DDR_SDRAM_CFG_MEM_EN 0x80000000
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#define SDRAM_CFG2_D_INIT 0x00000010
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#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
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#define SDRAM_CFG2_FRC_SR 0x80000000
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#define SDRAM_CFG_BI 0x00000001
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#define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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/* CPLD */
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#define CFG_SYS_CPLD_BASE 0x7fb00000
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#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE
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#define CFG_SYS_FPGA_CSPR_EXT (0x0)
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#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/* CPLD Timing parameters for IFC GPCM */
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#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
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FTIM0_GPCM_TEADC(0xf) | \
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FTIM0_GPCM_TEAHC(0xf))
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#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0xff))
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#define CFG_SYS_FPGA_FTIM3 0x0
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#define CFG_SYS_CSPR0_EXT CFG_SYS_FPGA_CSPR_EXT
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#define CFG_SYS_CSPR0 CFG_SYS_FPGA_CSPR
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#define CFG_SYS_AMASK0 CFG_SYS_FPGA_AMASK
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#define CFG_SYS_CSOR0 CFG_SYS_FPGA_CSOR
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#define CFG_SYS_CS0_FTIM0 CFG_SYS_FPGA_FTIM0
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#define CFG_SYS_CS0_FTIM1 CFG_SYS_FPGA_FTIM1
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#define CFG_SYS_CS0_FTIM2 CFG_SYS_FPGA_FTIM2
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#define CFG_SYS_CS0_FTIM3 CFG_SYS_FPGA_FTIM3
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/*
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* Serial Port
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*/
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#define CFG_SYS_NS16550_CLK get_serial_clock()
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/*
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* I2C
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*/
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/*
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* MMC
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*/
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/* SPI */
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#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
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#define CFG_SMP_PEN_ADDR 0x01ee0200
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#define HWCONFIG_BUFFER_SIZE 256
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#define CFG_EXTRA_ENV_SETTINGS \
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"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
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"initrd_high=0xffffffff\0"
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_SYS_BOOTMAPSZ (256 << 20)
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#include <asm/fsl_secure_boot.h>
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#endif
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