581 lines
18 KiB
C
581 lines
18 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025 MediaTek Inc.
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* Author: Qiqi Wang <qiqi.wang@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_CLK_MT8189_H
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#define _DT_BINDINGS_CLK_MT8189_H
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/* TOPCKGEN */
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#define CLK_TOP_AXI_SEL 0
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#define CLK_TOP_AXI_PERI_SEL 1
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#define CLK_TOP_AXI_U_SEL 2
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#define CLK_TOP_BUS_AXIMEM_SEL 3
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#define CLK_TOP_DISP0_SEL 4
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#define CLK_TOP_MMINFRA_SEL 5
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#define CLK_TOP_UART_SEL 6
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#define CLK_TOP_SPI0_SEL 7
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#define CLK_TOP_SPI1_SEL 8
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#define CLK_TOP_SPI2_SEL 9
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#define CLK_TOP_SPI3_SEL 10
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#define CLK_TOP_SPI4_SEL 11
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#define CLK_TOP_SPI5_SEL 12
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#define CLK_TOP_MSDC_MACRO_0P_SEL 13
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#define CLK_TOP_MSDC50_0_HCLK_SEL 14
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#define CLK_TOP_MSDC50_0_SEL 15
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#define CLK_TOP_AES_MSDCFDE_SEL 16
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#define CLK_TOP_MSDC_MACRO_1P_SEL 17
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#define CLK_TOP_MSDC30_1_SEL 18
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#define CLK_TOP_MSDC30_1_HCLK_SEL 19
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#define CLK_TOP_MSDC_MACRO_2P_SEL 20
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#define CLK_TOP_MSDC30_2_SEL 21
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#define CLK_TOP_MSDC30_2_HCLK_SEL 22
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#define CLK_TOP_AUD_INTBUS_SEL 23
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#define CLK_TOP_ATB_SEL 24
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#define CLK_TOP_DISP_PWM_SEL 25
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#define CLK_TOP_USB_TOP_P0_SEL 26
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#define CLK_TOP_USB_XHCI_P0_SEL 27
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#define CLK_TOP_USB_TOP_P1_SEL 28
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#define CLK_TOP_USB_XHCI_P1_SEL 29
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#define CLK_TOP_USB_TOP_P2_SEL 30
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#define CLK_TOP_USB_XHCI_P2_SEL 31
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#define CLK_TOP_USB_TOP_P3_SEL 32
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#define CLK_TOP_USB_XHCI_P3_SEL 33
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#define CLK_TOP_USB_TOP_P4_SEL 34
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#define CLK_TOP_USB_XHCI_P4_SEL 35
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#define CLK_TOP_I2C_SEL 36
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#define CLK_TOP_SENINF_SEL 37
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#define CLK_TOP_SENINF1_SEL 38
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#define CLK_TOP_AUD_ENGEN1_SEL 39
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#define CLK_TOP_AUD_ENGEN2_SEL 40
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#define CLK_TOP_AES_UFSFDE_SEL 41
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#define CLK_TOP_U_SEL 42
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#define CLK_TOP_U_MBIST_SEL 43
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#define CLK_TOP_AUD_1_SEL 44
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#define CLK_TOP_AUD_2_SEL 45
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#define CLK_TOP_VENC_SEL 46
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#define CLK_TOP_VDEC_SEL 47
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#define CLK_TOP_PWM_SEL 48
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#define CLK_TOP_AUDIO_H_SEL 49
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#define CLK_TOP_MCUPM_SEL 50
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#define CLK_TOP_MEM_SUB_SEL 51
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#define CLK_TOP_MEM_SUB_PERI_SEL 52
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#define CLK_TOP_MEM_SUB_U_SEL 53
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#define CLK_TOP_EMI_N_SEL 54
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#define CLK_TOP_DSI_OCC_SEL 55
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#define CLK_TOP_AP2CONN_HOST_SEL 56
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#define CLK_TOP_IMG1_SEL 57
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#define CLK_TOP_IPE_SEL 58
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#define CLK_TOP_CAM_SEL 59
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#define CLK_TOP_CAMTM_SEL 60
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#define CLK_TOP_DSP_SEL 61
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#define CLK_TOP_SR_PKA_SEL 62
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#define CLK_TOP_DXCC_SEL 63
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#define CLK_TOP_MFG_REF_SEL 64
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#define CLK_TOP_MDP0_SEL 65
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#define CLK_TOP_DP_SEL 66
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#define CLK_TOP_EDP_SEL 67
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#define CLK_TOP_EDP_FAVT_SEL 68
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#define CLK_TOP_ETH_250M_SEL 69
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#define CLK_TOP_ETH_62P4M_PTP_SEL 70
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#define CLK_TOP_ETH_50M_RMII_SEL 71
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#define CLK_TOP_SFLASH_SEL 72
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#define CLK_TOP_GCPU_SEL 73
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#define CLK_TOP_MAC_TL_SEL 74
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#define CLK_TOP_VDSTX_DG_CTS_SEL 75
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#define CLK_TOP_PLL_DPIX_SEL 76
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#define CLK_TOP_ECC_SEL 77
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#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78
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#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79
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#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80
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#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81
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#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82
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#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83
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#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84
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#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85
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#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86
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#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87
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#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88
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#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89
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#define CLK_TOP_APLL_FMI2S_MCK_SEL 90
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#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91
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#define CLK_TOP_MFG_SEL_MFGPLL 92
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#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93
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#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94
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#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95
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#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96
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#define CLK_TOP_APLL12_CK_DIV_FMI2S 97
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#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98
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#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99
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#define CLK_TOP_MAINPLL_D3 100
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#define CLK_TOP_MAINPLL_D4 101
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#define CLK_TOP_MAINPLL_D4_D2 102
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#define CLK_TOP_MAINPLL_D4_D4 103
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#define CLK_TOP_MAINPLL_D4_D8 104
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#define CLK_TOP_MAINPLL_D5 105
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#define CLK_TOP_MAINPLL_D5_D2 106
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#define CLK_TOP_MAINPLL_D5_D4 107
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#define CLK_TOP_MAINPLL_D5_D8 108
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#define CLK_TOP_MAINPLL_D6 109
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#define CLK_TOP_MAINPLL_D6_D2 110
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#define CLK_TOP_MAINPLL_D6_D4 111
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#define CLK_TOP_MAINPLL_D6_D8 112
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#define CLK_TOP_MAINPLL_D7 113
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#define CLK_TOP_MAINPLL_D7_D2 114
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#define CLK_TOP_MAINPLL_D7_D4 115
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#define CLK_TOP_MAINPLL_D7_D8 116
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#define CLK_TOP_MAINPLL_D9 117
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#define CLK_TOP_UNIVPLL_D2 118
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#define CLK_TOP_UNIVPLL_D3 119
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#define CLK_TOP_UNIVPLL_D4 120
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#define CLK_TOP_UNIVPLL_D4_D2 121
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#define CLK_TOP_UNIVPLL_D4_D4 122
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#define CLK_TOP_UNIVPLL_D4_D8 123
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#define CLK_TOP_UNIVPLL_D5 124
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#define CLK_TOP_UNIVPLL_D5_D2 125
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#define CLK_TOP_UNIVPLL_D5_D4 126
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#define CLK_TOP_UNIVPLL_D6 127
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#define CLK_TOP_UNIVPLL_D6_D2 128
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#define CLK_TOP_UNIVPLL_D6_D4 129
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#define CLK_TOP_UNIVPLL_D6_D8 130
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#define CLK_TOP_UNIVPLL_D6_D16 131
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#define CLK_TOP_UNIVPLL_D7 132
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#define CLK_TOP_UNIVPLL_D7_D2 133
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#define CLK_TOP_UNIVPLL_D7_D3 134
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#define CLK_TOP_LVDSTX_DG_CTS 135
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#define CLK_TOP_UNIVPLL_192M 136
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#define CLK_TOP_UNIVPLL_192M_D2 137
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#define CLK_TOP_UNIVPLL_192M_D4 138
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#define CLK_TOP_UNIVPLL_192M_D8 139
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#define CLK_TOP_UNIVPLL_192M_D10 140
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#define CLK_TOP_UNIVPLL_192M_D16 141
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#define CLK_TOP_UNIVPLL_192M_D32 142
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#define CLK_TOP_APLL1_D2 143
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#define CLK_TOP_APLL1_D4 144
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#define CLK_TOP_APLL1_D8 145
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#define CLK_TOP_APLL1_D3 146
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#define CLK_TOP_APLL2_D2 147
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#define CLK_TOP_APLL2_D4 148
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#define CLK_TOP_APLL2_D8 149
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#define CLK_TOP_APLL2_D3 150
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#define CLK_TOP_MMPLL_D4 151
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#define CLK_TOP_MMPLL_D4_D2 152
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#define CLK_TOP_MMPLL_D4_D4 153
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#define CLK_TOP_VPLL_DPIX 154
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#define CLK_TOP_MMPLL_D5 155
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#define CLK_TOP_MMPLL_D5_D2 156
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#define CLK_TOP_MMPLL_D5_D4 157
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#define CLK_TOP_MMPLL_D6 158
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#define CLK_TOP_MMPLL_D6_D2 159
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#define CLK_TOP_MMPLL_D7 160
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#define CLK_TOP_MMPLL_D9 161
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#define CLK_TOP_TVDPLL1_D2 162
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#define CLK_TOP_TVDPLL1_D4 163
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#define CLK_TOP_TVDPLL1_D8 164
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#define CLK_TOP_TVDPLL1_D16 165
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#define CLK_TOP_TVDPLL2_D2 166
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#define CLK_TOP_TVDPLL2_D4 167
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#define CLK_TOP_TVDPLL2_D8 168
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#define CLK_TOP_TVDPLL2_D16 169
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#define CLK_TOP_ETHPLL_D2 170
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#define CLK_TOP_ETHPLL_D8 171
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#define CLK_TOP_ETHPLL_D10 172
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#define CLK_TOP_MSDCPLL_D2 173
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#define CLK_TOP_VOWPLL 174
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#define CLK_TOP_UFSPLL_D2 175
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#define CLK_TOP_F26M_CK_D2 176
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#define CLK_TOP_OSC_D2 177
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#define CLK_TOP_OSC_D4 178
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#define CLK_TOP_OSC_D8 179
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#define CLK_TOP_OSC_D16 180
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#define CLK_TOP_OSC_D3 181
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#define CLK_TOP_OSC_D7 182
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#define CLK_TOP_OSC_D10 183
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#define CLK_TOP_OSC_D20 184
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#define CLK_TOP_FMCNT_P0_EN 185
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#define CLK_TOP_FMCNT_P1_EN 186
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#define CLK_TOP_FMCNT_P2_EN 187
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#define CLK_TOP_FMCNT_P3_EN 188
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#define CLK_TOP_FMCNT_P4_EN 189
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#define CLK_TOP_USB_F26M_CK_EN 190
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#define CLK_TOP_SSPXTP_F26M_CK_EN 191
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#define CLK_TOP_USB2_PHY_RF_P0_EN 192
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#define CLK_TOP_USB2_PHY_RF_P1_EN 193
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#define CLK_TOP_USB2_PHY_RF_P2_EN 194
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#define CLK_TOP_USB2_PHY_RF_P3_EN 195
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#define CLK_TOP_USB2_PHY_RF_P4_EN 196
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#define CLK_TOP_USB2_26M_CK_P0_EN 197
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#define CLK_TOP_USB2_26M_CK_P1_EN 198
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#define CLK_TOP_USB2_26M_CK_P2_EN 199
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#define CLK_TOP_USB2_26M_CK_P3_EN 200
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#define CLK_TOP_USB2_26M_CK_P4_EN 201
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#define CLK_TOP_F26M_CK_EN 202
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#define CLK_TOP_AP2CON_EN 203
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#define CLK_TOP_EINT_N_EN 204
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#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 205
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#define CLK_TOP_DRAMULP_CK_EN 206
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#define CLK_TOP_EINT_E_EN 207
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#define CLK_TOP_EINT_W_EN 208
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#define CLK_TOP_EINT_S_EN 209
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/* INFRACFG_AO */
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#define CLK_IFRAO_CQ_DMA_FPC 0
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#define CLK_IFRAO_DEBUGSYS 1
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#define CLK_IFRAO_DBG_TRACE 2
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#define CLK_IFRAO_CQ_DMA 3
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL_LL 0
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#define CLK_APMIXED_ARMPLL_BL 1
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#define CLK_APMIXED_CCIPLL 2
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#define CLK_APMIXED_MAINPLL 3
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#define CLK_APMIXED_UNIVPLL 4
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#define CLK_APMIXED_MMPLL 5
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#define CLK_APMIXED_MFGPLL 6
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#define CLK_APMIXED_APLL1 7
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#define CLK_APMIXED_APLL2 8
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#define CLK_APMIXED_EMIPLL 9
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#define CLK_APMIXED_APUPLL2 10
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#define CLK_APMIXED_APUPLL 11
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#define CLK_APMIXED_TVDPLL1 12
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#define CLK_APMIXED_TVDPLL2 13
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#define CLK_APMIXED_ETHPLL 14
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#define CLK_APMIXED_MSDCPLL 15
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#define CLK_APMIXED_UFSPLL 16
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/* PERICFG_AO */
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#define CLK_PERAO_UART0 0
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#define CLK_PERAO_UART1 1
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#define CLK_PERAO_UART2 2
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#define CLK_PERAO_UART3 3
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#define CLK_PERAO_PWM_H 4
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#define CLK_PERAO_PWM_B 5
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#define CLK_PERAO_PWM_FB1 6
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#define CLK_PERAO_PWM_FB2 7
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#define CLK_PERAO_PWM_FB3 8
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#define CLK_PERAO_PWM_FB4 9
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#define CLK_PERAO_DISP_PWM0 10
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#define CLK_PERAO_DISP_PWM1 11
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#define CLK_PERAO_SPI0_B 12
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#define CLK_PERAO_SPI1_B 13
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#define CLK_PERAO_SPI2_B 14
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#define CLK_PERAO_SPI3_B 15
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#define CLK_PERAO_SPI4_B 16
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#define CLK_PERAO_SPI5_B 17
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#define CLK_PERAO_SPI0_H 18
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#define CLK_PERAO_SPI1_H 19
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#define CLK_PERAO_SPI2_H 20
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#define CLK_PERAO_SPI3_H 21
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#define CLK_PERAO_SPI4_H 22
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#define CLK_PERAO_SPI5_H 23
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#define CLK_PERAO_AXI 24
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#define CLK_PERAO_AHB_APB 25
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#define CLK_PERAO_TL 26
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#define CLK_PERAO_REF 27
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#define CLK_PERAO_I2C 28
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#define CLK_PERAO_DMA_B 29
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#define CLK_PERAO_SSUSB0_REF 30
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#define CLK_PERAO_SSUSB0_FRMCNT 31
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#define CLK_PERAO_SSUSB0_SYS 32
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#define CLK_PERAO_SSUSB0_XHCI 33
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#define CLK_PERAO_SSUSB0_F 34
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#define CLK_PERAO_SSUSB0_H 35
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#define CLK_PERAO_SSUSB1_REF 36
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#define CLK_PERAO_SSUSB1_FRMCNT 37
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#define CLK_PERAO_SSUSB1_SYS 38
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#define CLK_PERAO_SSUSB1_XHCI 39
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#define CLK_PERAO_SSUSB1_F 40
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#define CLK_PERAO_SSUSB1_H 41
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#define CLK_PERAO_SSUSB2_REF 42
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#define CLK_PERAO_SSUSB2_FRMCNT 43
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#define CLK_PERAO_SSUSB2_SYS 44
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#define CLK_PERAO_SSUSB2_XHCI 45
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#define CLK_PERAO_SSUSB2_F 46
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#define CLK_PERAO_SSUSB2_H 47
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#define CLK_PERAO_SSUSB3_REF 48
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#define CLK_PERAO_SSUSB3_FRMCNT 49
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#define CLK_PERAO_SSUSB3_SYS 50
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#define CLK_PERAO_SSUSB3_XHCI 51
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#define CLK_PERAO_SSUSB3_F 52
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#define CLK_PERAO_SSUSB3_H 53
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#define CLK_PERAO_SSUSB4_REF 54
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#define CLK_PERAO_SSUSB4_FRMCNT 55
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#define CLK_PERAO_SSUSB4_SYS 56
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#define CLK_PERAO_SSUSB4_XHCI 57
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#define CLK_PERAO_SSUSB4_F 58
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#define CLK_PERAO_SSUSB4_H 59
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#define CLK_PERAO_MSDC0 60
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#define CLK_PERAO_MSDC0_H 61
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#define CLK_PERAO_MSDC0_FAES 62
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#define CLK_PERAO_MSDC0_MST_F 63
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#define CLK_PERAO_MSDC0_SLV_H 64
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#define CLK_PERAO_MSDC1 65
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#define CLK_PERAO_MSDC1_H 66
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#define CLK_PERAO_MSDC1_MST_F 67
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#define CLK_PERAO_MSDC1_SLV_H 68
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#define CLK_PERAO_MSDC2 69
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#define CLK_PERAO_MSDC2_H 70
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#define CLK_PERAO_MSDC2_MST_F 71
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#define CLK_PERAO_MSDC2_SLV_H 72
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#define CLK_PERAO_SFLASH 73
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#define CLK_PERAO_SFLASH_F 74
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#define CLK_PERAO_SFLASH_H 75
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#define CLK_PERAO_SFLASH_P 76
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#define CLK_PERAO_AUDIO0 77
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#define CLK_PERAO_AUDIO1 78
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#define CLK_PERAO_AUDIO2 79
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#define CLK_PERAO_AUXADC_26M 80
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/* UFSCFG_AO_REG */
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#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0
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#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1
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#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2
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#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3
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#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4
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#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5
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/* UFSCFG_PDN_REG */
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#define CLK_UFSCFG_REG_UFSHCI_UFS 0
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#define CLK_UFSCFG_REG_UFSHCI_AES 1
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#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2
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#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3
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/* IMP_IIC_WRAP_WS */
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#define CLK_IMPWS_I2C2 0
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/* IMP_IIC_WRAP_E */
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#define CLK_IMPE_I2C0 0
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#define CLK_IMPE_I2C1 1
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/* IMP_IIC_WRAP_S */
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#define CLK_IMPS_I2C3 0
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#define CLK_IMPS_I2C4 1
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#define CLK_IMPS_I2C5 2
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#define CLK_IMPS_I2C6 3
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/* IMP_IIC_WRAP_EN */
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#define CLK_IMPEN_I2C7 0
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#define CLK_IMPEN_I2C8 1
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/* MFG */
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#define CLK_MFG_BG3D 0
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/* DISPSYS_CONFIG */
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#define CLK_MM_DISP_OVL0_4L 0
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#define CLK_MM_DISP_OVL1_4L 1
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#define CLK_MM_VPP_RSZ0 2
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#define CLK_MM_VPP_RSZ1 3
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#define CLK_MM_DISP_RDMA0 4
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#define CLK_MM_DISP_RDMA1 5
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#define CLK_MM_DISP_COLOR0 6
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#define CLK_MM_DISP_COLOR1 7
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#define CLK_MM_DISP_CCORR0 8
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#define CLK_MM_DISP_CCORR1 9
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#define CLK_MM_DISP_CCORR2 10
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#define CLK_MM_DISP_CCORR3 11
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#define CLK_MM_DISP_AAL0 12
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#define CLK_MM_DISP_AAL1 13
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#define CLK_MM_DISP_GAMMA0 14
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#define CLK_MM_DISP_GAMMA1 15
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#define CLK_MM_DISP_DITHER0 16
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#define CLK_MM_DISP_DITHER1 17
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#define CLK_MM_DISP_DSC_WRAP0 18
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#define CLK_MM_VPP_MERGE0 19
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#define CLK_MMSYS_0_DISP_DVO 20
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#define CLK_MMSYS_0_DISP_DSI0 21
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#define CLK_MM_DP_INTF0 22
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#define CLK_MM_DPI0 23
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#define CLK_MM_DISP_WDMA0 24
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#define CLK_MM_DISP_WDMA1 25
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#define CLK_MM_DISP_FAKE_ENG0 26
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#define CLK_MM_DISP_FAKE_ENG1 27
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#define CLK_MM_SMI_LARB 28
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#define CLK_MM_DISP_MUTEX0 29
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#define CLK_MM_DIPSYS_CONFIG 30
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#define CLK_MM_DUMMY 31
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#define CLK_MMSYS_1_DISP_DSI0 32
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#define CLK_MMSYS_1_LVDS_ENCODER 33
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#define CLK_MMSYS_1_DPI0 34
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#define CLK_MMSYS_1_DISP_DVO 35
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#define CLK_MM_DP_INTF 36
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#define CLK_MMSYS_1_LVDS_ENCODER_CTS 37
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#define CLK_MMSYS_1_DISP_DVO_AVT 38
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/* IMGSYS1 */
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#define CLK_IMGSYS1_LARB9 0
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#define CLK_IMGSYS1_LARB11 1
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#define CLK_IMGSYS1_DIP 2
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#define CLK_IMGSYS1_GALS 3
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/* IMGSYS2 */
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#define CLK_IMGSYS2_LARB9 0
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#define CLK_IMGSYS2_LARB11 1
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#define CLK_IMGSYS2_MFB 2
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#define CLK_IMGSYS2_WPE 3
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#define CLK_IMGSYS2_MSS 4
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#define CLK_IMGSYS2_GALS 5
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/* VDEC_CORE */
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#define CLK_VDEC_CORE_LARB_CKEN 0
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#define CLK_VDEC_CORE_VDEC_CKEN 1
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#define CLK_VDEC_CORE_VDEC_ACTIVE 2
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/* VENC_GCON */
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#define CLK_VEN1_CKE0_LARB 0
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#define CLK_VEN1_CKE1_VENC 1
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#define CLK_VEN1_CKE2_JPGENC 2
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#define CLK_VEN1_CKE3_JPGDEC 3
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#define CLK_VEN1_CKE4_JPGDEC_C1 4
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#define CLK_VEN1_CKE5_GALS 5
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#define CLK_VEN1_CKE6_GALS_SRAM 6
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/* VLPCFG_REG */
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#define CLK_VLPCFG_REG_SCP 0
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#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1
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#define CLK_VLPCFG_REG_DPMSRCK_TEST 2
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#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3
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#define CLK_VLPCFG_REG_DPMSRULP_TEST 4
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#define CLK_VLPCFG_REG_SPMI_P_MST 5
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#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6
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#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7
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#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8
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#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9
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#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10
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#define CLK_VLPCFG_REG_DVFSRC 11
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#define CLK_VLPCFG_REG_PWM_VLP 12
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#define CLK_VLPCFG_REG_SRCK 13
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#define CLK_VLPCFG_REG_SSPM_F26M 14
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#define CLK_VLPCFG_REG_SSPM_F32K 15
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#define CLK_VLPCFG_REG_SSPM_ULPOSC 16
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#define CLK_VLPCFG_REG_VLP_32K_COM 17
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#define CLK_VLPCFG_REG_VLP_26M_COM 18
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/* VLP_CKSYS */
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#define CLK_VLP_CK_SCP_SEL 0
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#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1
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#define CLK_VLP_CK_SPMI_P_MST_SEL 2
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#define CLK_VLP_CK_DVFSRC_SEL 3
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#define CLK_VLP_CK_PWM_VLP_SEL 4
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#define CLK_VLP_CK_AXI_VLP_SEL 5
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#define CLK_VLP_CK_SYSTIMER_26M_SEL 6
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#define CLK_VLP_CK_SSPM_SEL 7
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#define CLK_VLP_CK_SSPM_F26M_SEL 8
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#define CLK_VLP_CK_SRCK_SEL 9
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#define CLK_VLP_CK_SCP_SPI_SEL 10
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#define CLK_VLP_CK_SCP_IIC_SEL 11
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#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12
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#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13
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#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14
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#define CLK_VLP_CK_APXGPT_26M_SEL 15
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#define CLK_VLP_CK_VADSP_SEL 16
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#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17
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#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18
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#define CLK_VLP_CK_CAMTG0_SEL 19
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#define CLK_VLP_CK_CAMTG1_SEL 20
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#define CLK_VLP_CK_CAMTG2_SEL 21
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#define CLK_VLP_CK_AUD_ADC_SEL 22
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#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23
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#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24
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#define CLK_VLP_CK_SEJ_13M_EN 25
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#define CLK_VLP_CK_SEJ_26M_EN 26
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#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 27
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/* SCP_IIC */
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#define CLK_SCP_IIC_I2C0_W1S 0
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#define CLK_SCP_IIC_I2C1_W1S 1
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/* SCP */
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#define CLK_SCP_SET_SPI0 0
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#define CLK_SCP_SET_SPI1 1
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/* CAMSYS_MAIN */
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#define CLK_CAM_M_LARB13 0
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#define CLK_CAM_M_LARB14 1
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#define CLK_CAM_M_CAMSYS_MAIN_CAM 2
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#define CLK_CAM_M_CAMSYS_MAIN_CAMTG 3
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#define CLK_CAM_M_SENINF 4
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#define CLK_CAM_M_CAMSV1 5
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#define CLK_CAM_M_CAMSV2 6
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#define CLK_CAM_M_CAMSV3 7
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#define CLK_CAM_M_FAKE_ENG 8
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#define CLK_CAM_M_CAM2MM_GALS 9
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#define CLK_CAM_M_CAMSV4 10
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#define CLK_CAM_M_PDA 11
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/* CAMSYS_RAWA */
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#define CLK_CAM_RA_CAMSYS_RAWA_LARBX 0
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#define CLK_CAM_RA_CAMSYS_RAWA_CAM 1
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#define CLK_CAM_RA_CAMSYS_RAWA_CAMTG 2
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/* CAMSYS_RAWB */
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#define CLK_CAM_RB_CAMSYS_RAWB_LARBX 0
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#define CLK_CAM_RB_CAMSYS_RAWB_CAM 1
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#define CLK_CAM_RB_CAMSYS_RAWB_CAMTG 2
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/* IPESYS */
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#define CLK_IPE_LARB19 0
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#define CLK_IPE_LARB20 1
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#define CLK_IPE_SMI_SUBCOM 2
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#define CLK_IPE_FD 3
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#define CLK_IPE_FE 4
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#define CLK_IPE_RSC 5
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#define CLK_IPESYS_GALS 6
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/* VLPCFG_AO_REG */
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#define CLK_VLPCFG_AO_APEINT_RX 0
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/* DVFSRC_TOP */
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#define CLK_DVFSRC_TOP_DVFSRC_EN 0
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/* MMINFRA_CONFIG */
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#define CLK_MMINFRA_GCE_D 0
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#define CLK_MMINFRA_GCE_M 1
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#define CLK_MMINFRA_SMI 2
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#define CLK_MMINFRA_GCE_26M 3
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/* GCE_D */
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#define CLK_GCE_D_TOP 0
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/* GCE_M */
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#define CLK_GCE_M_TOP 0
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/* MDPSYS_CONFIG */
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#define CLK_MDP_MUTEX0 0
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#define CLK_MDP_APB_BUS 1
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#define CLK_MDP_SMI0 2
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#define CLK_MDP_RDMA0 3
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#define CLK_MDP_RDMA2 4
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#define CLK_MDP_HDR0 5
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#define CLK_MDP_AAL0 6
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#define CLK_MDP_RSZ0 7
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#define CLK_MDP_TDSHP0 8
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#define CLK_MDP_COLOR0 9
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#define CLK_MDP_WROT0 10
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#define CLK_MDP_FAKE_ENG0 11
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#define CLK_MDPSYS_CONFIG 12
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#define CLK_MDP_RDMA1 13
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#define CLK_MDP_RDMA3 14
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#define CLK_MDP_HDR1 15
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#define CLK_MDP_AAL1 16
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#define CLK_MDP_RSZ1 17
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#define CLK_MDP_TDSHP1 18
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#define CLK_MDP_COLOR1 19
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#define CLK_MDP_WROT1 20
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#define CLK_MDP_RSZ2 21
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#define CLK_MDP_WROT2 22
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#define CLK_MDP_RSZ3 23
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#define CLK_MDP_WROT3 24
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#define CLK_MDP_BIRSZ0 25
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#define CLK_MDP_BIRSZ1 26
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/* DBGAO */
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#define CLK_DBGAO_ATB_EN 0
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/* DEM */
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#define CLK_DEM_ATB_EN 0
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#define CLK_DEM_BUSCLK_EN 1
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#define CLK_DEM_SYSCLK_EN 2
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#endif /* _DT_BINDINGS_CLK_MT8189_H */
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