226 lines
8.5 KiB
C
226 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2026 MediaTek Inc. All Rights Reserved.
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* Author: Bo-Chen Chen <rex-bc.chen@mediatek.com>
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*/
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#ifndef __MT6359_H_
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#define __MT6359_H_
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#define MT6359_REGULATOR_DRIVER "mt6359_regulator"
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enum {
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MT6359_ID_VS1 = 0,
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MT6359_ID_VGPU11,
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MT6359_ID_VMODEM,
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MT6359_ID_VPU,
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MT6359_ID_VCORE,
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MT6359_ID_VS2,
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MT6359_ID_VPA,
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MT6359_ID_VPROC2,
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MT6359_ID_VPROC1,
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MT6359_ID_VCORE_SSHUB,
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MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB,
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MT6359_ID_VAUD18 = 10,
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MT6359_ID_VSIM1,
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MT6359_ID_VIBR,
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MT6359_ID_VRF12,
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MT6359_ID_VUSB,
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MT6359_ID_VSRAM_PROC2,
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MT6359_ID_VIO18,
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MT6359_ID_VCAMIO,
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MT6359_ID_VCN18,
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MT6359_ID_VFE28,
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MT6359_ID_VCN13,
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MT6359_ID_VCN33_1_BT,
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MT6359_ID_VCN33_1_WIFI,
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MT6359_ID_VAUX18,
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MT6359_ID_VSRAM_OTHERS,
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MT6359_ID_VEFUSE,
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MT6359_ID_VXO22,
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MT6359_ID_VRFCK,
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MT6359_ID_VBIF28,
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MT6359_ID_VIO28,
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MT6359_ID_VEMC,
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MT6359_ID_VCN33_2_BT,
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MT6359_ID_VCN33_2_WIFI,
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MT6359_ID_VA12,
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MT6359_ID_VA09,
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MT6359_ID_VRF18,
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MT6359_ID_VSRAM_MD,
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MT6359_ID_VUFS,
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MT6359_ID_VM18,
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MT6359_ID_VBBCK,
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MT6359_ID_VSRAM_PROC1,
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MT6359_ID_VSIM2,
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MT6359_ID_VSRAM_OTHERS_SSHUB,
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MT6359_ID_RG_MAX,
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};
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/* PMIC Registers */
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#define MT6359_BUCK_VPU_CON0 0x1488
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#define MT6359_BUCK_VPU_DBG1 0x14a8
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#define MT6359_BUCK_VPU_ELR0 0x14ac
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#define MT6359_BUCK_VCORE_CON0 0x1508
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#define MT6359_BUCK_VCORE_DBG1 0x1528
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#define MT6359_BUCK_VGPU11_CON0 0x1588
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#define MT6359_BUCK_VGPU11_DBG1 0x15a8
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#define MT6359_BUCK_VMODEM_CON0 0x1688
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#define MT6359_BUCK_VMODEM_DBG1 0x16a8
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#define MT6359_BUCK_VMODEM_ELR0 0x16ae
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#define MT6359_BUCK_VPROC1_CON0 0x1708
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#define MT6359_BUCK_VPROC1_DBG1 0x1728
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#define MT6359_BUCK_VPROC1_ELR0 0x172e
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#define MT6359_BUCK_VPROC2_CON0 0x1788
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#define MT6359_BUCK_VPROC2_DBG1 0x17a8
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#define MT6359_BUCK_VPROC2_ELR0 0x17b2
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#define MT6359_BUCK_VS1_CON0 0x1808
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#define MT6359_BUCK_VS1_DBG1 0x1828
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#define MT6359_BUCK_VS1_ELR0 0x1834
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#define MT6359_BUCK_VS2_CON0 0x1888
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#define MT6359_BUCK_VS2_DBG1 0x18a8
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#define MT6359_BUCK_VS2_ELR0 0x18b4
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#define MT6359_BUCK_VPA_CON0 0x1908
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#define MT6359_BUCK_VPA_CON1 0x190e
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#define MT6359_BUCK_VPA_DBG1 0x1916
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#define MT6359_VGPUVCORE_ANA_CON2 0x198e
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#define MT6359_VGPUVCORE_ANA_CON13 0x19a4
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#define MT6359_VPROC1_ANA_CON3 0x19b2
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#define MT6359_VPROC2_ANA_CON3 0x1a0e
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#define MT6359_VMODEM_ANA_CON3 0x1a1a
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#define MT6359_VPU_ANA_CON3 0x1a26
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#define MT6359_VS1_ANA_CON0 0x1a2c
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#define MT6359_VS2_ANA_CON0 0x1a34
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#define MT6359_VPA_ANA_CON0 0x1a3c
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#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0
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#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0
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#define MT6359_RG_BUCK_VPU_LP_SHIFT 1
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#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1
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#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0
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#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0
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#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0
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#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1
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#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1
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#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0
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#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0
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#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1
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#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1
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#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0
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#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0
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#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1
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#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1
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#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0
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#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0
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#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0
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#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1
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#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1
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#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0
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#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0
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#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0
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#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1
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#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1
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#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0
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#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0
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#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0
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#define MT6359_RG_BUCK_VS1_LP_SHIFT 1
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#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1
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#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0
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#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0
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#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0
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#define MT6359_RG_BUCK_VS2_LP_SHIFT 1
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#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1
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#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0
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#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F
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#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0
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#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0
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#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0
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#define MT6359_RG_BUCK_VPA_LP_SHIFT 1
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#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1
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#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F
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#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0
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#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1
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#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2
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#define MT6359_RG_VGPU11_FCCM_SHIFT 9
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#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13
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#define MT6359_RG_VCORE_FCCM_SHIFT 5
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#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3
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#define MT6359_RG_VPROC1_FCCM_SHIFT 1
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#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3
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#define MT6359_RG_VPROC2_FCCM_SHIFT 1
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#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3
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#define MT6359_RG_VMODEM_FCCM_SHIFT 1
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#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3
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#define MT6359_RG_VPU_FCCM_SHIFT 1
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#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0
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#define MT6359_RG_VS1_FPWM_SHIFT 3
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#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0
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#define MT6359_RG_VS2_FPWM_SHIFT 3
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#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0
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#define MT6359_RG_VPA_MODESET_SHIFT 1
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#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F
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#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0
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#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F
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#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0
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#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
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#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0
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#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F
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#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0
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#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0
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#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15
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#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
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#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1
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#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF
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#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8
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#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF
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#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8
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#define MT6359_RG_VSIM1_VOSEL_MASK 0xF
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#define MT6359_RG_VSIM1_VOSEL_SHIFT 8
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#define MT6359_RG_VSIM2_VOSEL_MASK 0xF
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#define MT6359_RG_VSIM2_VOSEL_SHIFT 8
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#define MT6359_RG_VIO28_VOSEL_MASK 0xF
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#define MT6359_RG_VIO28_VOSEL_SHIFT 8
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#define MT6359_RG_VIBR_VOSEL_MASK 0xF
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#define MT6359_RG_VIBR_VOSEL_SHIFT 8
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#define MT6359_RG_VRF18_VOSEL_MASK 0xF
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#define MT6359_RG_VRF18_VOSEL_SHIFT 8
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#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF
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#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8
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#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF
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#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8
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#define MT6359_RG_VIO18_VOSEL_MASK 0xF
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#define MT6359_RG_VIO18_VOSEL_SHIFT 8
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#define MT6359_RG_VM18_VOSEL_MASK 0xF
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#define MT6359_RG_VM18_VOSEL_SHIFT 8
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#define MT6359_RG_VUFS_VOSEL_MASK 0xF
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#define MT6359_RG_VUFS_VOSEL_SHIFT 8
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#define MT6359_RG_VRF12_VOSEL_MASK 0xF
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#define MT6359_RG_VRF12_VOSEL_SHIFT 8
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#define MT6359_RG_VCN13_VOSEL_MASK 0xF
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#define MT6359_RG_VCN13_VOSEL_SHIFT 8
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#define MT6359_RG_VA09_VOSEL_MASK 0xF
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#define MT6359_RG_VA09_VOSEL_SHIFT 8
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#define MT6359_RG_VA12_VOSEL_MASK 0xF
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#define MT6359_RG_VA12_VOSEL_SHIFT 8
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#define MT6359_RG_VXO22_VOSEL_MASK 0xF
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#define MT6359_RG_VXO22_VOSEL_SHIFT 8
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#define MT6359_RG_VRFCK_VOSEL_MASK 0xF
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#define MT6359_RG_VRFCK_VOSEL_SHIFT 8
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#endif
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