382 lines
12 KiB
C
382 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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*
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* Configuration settings for the STM32MP13x CPU
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*/
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#ifndef STM32MP13_RCC_H
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#define STM32MP13_RCC_H
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/* RCC registers */
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#define RCC_SECCFGR 0x0
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#define RCC_MP_SREQSETR 0x100
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#define RCC_MP_SREQCLRR 0x104
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#define RCC_MP_APRSTCR 0x108
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#define RCC_MP_APRSTSR 0x10c
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#define RCC_PWRLPDLYCR 0x110
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#define RCC_MP_GRSTCSETR 0x114
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#define RCC_BR_RSTSCLRR 0x118
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#define RCC_MP_RSTSSETR 0x11c
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#define RCC_MP_RSTSCLRR 0x120
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#define RCC_MP_IWDGFZSETR 0x124
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#define RCC_MP_IWDGFZCLRR 0x128
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#define RCC_MP_CIER 0x200
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#define RCC_MP_CIFR 0x204
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#define RCC_BDCR 0x400
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#define RCC_RDLSICR 0x404
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#define RCC_OCENSETR 0x420
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#define RCC_OCENCLRR 0x424
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#define RCC_OCRDYR 0x428
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#define RCC_HSICFGR 0x440
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#define RCC_CSICFGR 0x444
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#define RCC_MCO1CFGR 0x460
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#define RCC_MCO2CFGR 0x464
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#define RCC_DBGCFGR 0x468
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#define RCC_RCK12SELR 0x480
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#define RCC_RCK3SELR 0x484
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#define RCC_RCK4SELR 0x488
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#define RCC_PLL1CR 0x4a0
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#define RCC_PLL1CFGR1 0x4a4
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#define RCC_PLL1CFGR2 0x4a8
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#define RCC_PLL1FRACR 0x4ac
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#define RCC_PLL1CSGR 0x4b0
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#define RCC_PLL2CR 0x4d0
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#define RCC_PLL2CFGR1 0x4d4
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#define RCC_PLL2CFGR2 0x4d8
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#define RCC_PLL2FRACR 0x4dc
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#define RCC_PLL2CSGR 0x4e0
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#define RCC_PLL3CR 0x500
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#define RCC_PLL3CFGR1 0x504
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#define RCC_PLL3CFGR2 0x508
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#define RCC_PLL3FRACR 0x50c
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#define RCC_PLL3CSGR 0x510
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#define RCC_PLL4CR 0x520
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#define RCC_PLL4CFGR1 0x524
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#define RCC_PLL4CFGR2 0x528
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#define RCC_PLL4FRACR 0x52c
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#define RCC_PLL4CSGR 0x530
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#define RCC_MPCKSELR 0x540
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#define RCC_ASSCKSELR 0x544
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#define RCC_MSSCKSELR 0x548
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#define RCC_CPERCKSELR 0x54c
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#define RCC_RTCDIVR 0x560
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#define RCC_MPCKDIVR 0x564
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#define RCC_AXIDIVR 0x568
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#define RCC_MLAHBDIVR 0x56c
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#define RCC_APB1DIVR 0x570
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#define RCC_APB2DIVR 0x574
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#define RCC_APB3DIVR 0x578
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#define RCC_APB4DIVR 0x57c
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#define RCC_APB5DIVR 0x580
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#define RCC_APB6DIVR 0x584
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#define RCC_TIMG1PRER 0x5a0
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#define RCC_TIMG2PRER 0x5a4
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#define RCC_TIMG3PRER 0x5a8
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#define RCC_DDRITFCR 0x5c0
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#define RCC_I2C12CKSELR 0x600
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#define RCC_I2C345CKSELR 0x604
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#define RCC_SPI2S1CKSELR 0x608
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#define RCC_SPI2S23CKSELR 0x60c
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#define RCC_SPI45CKSELR 0x610
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#define RCC_UART12CKSELR 0x614
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#define RCC_UART35CKSELR 0x618
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#define RCC_UART4CKSELR 0x61c
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#define RCC_UART6CKSELR 0x620
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#define RCC_UART78CKSELR 0x624
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#define RCC_LPTIM1CKSELR 0x628
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#define RCC_LPTIM23CKSELR 0x62c
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#define RCC_LPTIM45CKSELR 0x630
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#define RCC_SAI1CKSELR 0x634
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#define RCC_SAI2CKSELR 0x638
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#define RCC_FDCANCKSELR 0x63c
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#define RCC_SPDIFCKSELR 0x640
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#define RCC_ADC12CKSELR 0x644
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#define RCC_SDMMC12CKSELR 0x648
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#define RCC_ETH12CKSELR 0x64c
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#define RCC_USBCKSELR 0x650
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#define RCC_QSPICKSELR 0x654
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#define RCC_FMCCKSELR 0x658
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#define RCC_RNG1CKSELR 0x65c
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#define RCC_STGENCKSELR 0x660
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#define RCC_DCMIPPCKSELR 0x664
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#define RCC_SAESCKSELR 0x668
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#define RCC_APB1RSTSETR 0x6a0
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#define RCC_APB1RSTCLRR 0x6a4
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#define RCC_APB2RSTSETR 0x6a8
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#define RCC_APB2RSTCLRR 0x6ac
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#define RCC_APB3RSTSETR 0x6b0
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#define RCC_APB3RSTCLRR 0x6b4
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#define RCC_APB4RSTSETR 0x6b8
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#define RCC_APB4RSTCLRR 0x6bc
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#define RCC_APB5RSTSETR 0x6c0
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#define RCC_APB5RSTCLRR 0x6c4
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#define RCC_APB6RSTSETR 0x6c8
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#define RCC_APB6RSTCLRR 0x6cc
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#define RCC_AHB2RSTSETR 0x6d0
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#define RCC_AHB2RSTCLRR 0x6d4
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#define RCC_AHB4RSTSETR 0x6e0
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#define RCC_AHB4RSTCLRR 0x6e4
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#define RCC_AHB5RSTSETR 0x6e8
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#define RCC_AHB5RSTCLRR 0x6ec
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#define RCC_AHB6RSTSETR 0x6f0
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#define RCC_AHB6RSTCLRR 0x6f4
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#define RCC_MP_APB1ENSETR 0x700
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#define RCC_MP_APB1ENCLRR 0x704
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#define RCC_MP_APB2ENSETR 0x708
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#define RCC_MP_APB2ENCLRR 0x70c
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#define RCC_MP_APB3ENSETR 0x710
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#define RCC_MP_APB3ENCLRR 0x714
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#define RCC_MP_S_APB3ENSETR 0x718
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#define RCC_MP_S_APB3ENCLRR 0x71c
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#define RCC_MP_NS_APB3ENSETR 0x720
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#define RCC_MP_NS_APB3ENCLRR 0x724
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#define RCC_MP_APB4ENSETR 0x728
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#define RCC_MP_APB4ENCLRR 0x72c
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#define RCC_MP_S_APB4ENSETR 0x730
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#define RCC_MP_S_APB4ENCLRR 0x734
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#define RCC_MP_NS_APB4ENSETR 0x738
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#define RCC_MP_NS_APB4ENCLRR 0x73c
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#define RCC_MP_APB5ENSETR 0x740
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#define RCC_MP_APB5ENCLRR 0x744
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#define RCC_MP_APB6ENSETR 0x748
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#define RCC_MP_APB6ENCLRR 0x74c
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#define RCC_MP_AHB2ENSETR 0x750
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#define RCC_MP_AHB2ENCLRR 0x754
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#define RCC_MP_AHB4ENSETR 0x760
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#define RCC_MP_AHB4ENCLRR 0x764
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#define RCC_MP_S_AHB4ENSETR 0x768
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#define RCC_MP_S_AHB4ENCLRR 0x76c
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#define RCC_MP_NS_AHB4ENSETR 0x770
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#define RCC_MP_NS_AHB4ENCLRR 0x774
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#define RCC_MP_AHB5ENSETR 0x778
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#define RCC_MP_AHB5ENCLRR 0x77c
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#define RCC_MP_AHB6ENSETR 0x780
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#define RCC_MP_AHB6ENCLRR 0x784
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#define RCC_MP_S_AHB6ENSETR 0x788
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#define RCC_MP_S_AHB6ENCLRR 0x78c
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#define RCC_MP_NS_AHB6ENSETR 0x790
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#define RCC_MP_NS_AHB6ENCLRR 0x794
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#define RCC_MP_APB1LPENSETR 0x800
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#define RCC_MP_APB1LPENCLRR 0x804
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#define RCC_MP_APB2LPENSETR 0x808
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#define RCC_MP_APB2LPENCLRR 0x80c
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#define RCC_MP_APB3LPENSETR 0x810
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#define RCC_MP_APB3LPENCLRR 0x814
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#define RCC_MP_S_APB3LPENSETR 0x818
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#define RCC_MP_S_APB3LPENCLRR 0x81c
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#define RCC_MP_NS_APB3LPENSETR 0x820
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#define RCC_MP_NS_APB3LPENCLRR 0x824
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#define RCC_MP_APB4LPENSETR 0x828
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#define RCC_MP_APB4LPENCLRR 0x82c
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#define RCC_MP_S_APB4LPENSETR 0x830
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#define RCC_MP_S_APB4LPENCLRR 0x834
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#define RCC_MP_NS_APB4LPENSETR 0x838
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#define RCC_MP_NS_APB4LPENCLRR 0x83c
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#define RCC_MP_APB5LPENSETR 0x840
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#define RCC_MP_APB5LPENCLRR 0x844
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#define RCC_MP_APB6LPENSETR 0x848
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#define RCC_MP_APB6LPENCLRR 0x84c
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#define RCC_MP_AHB2LPENSETR 0x850
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#define RCC_MP_AHB2LPENCLRR 0x854
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#define RCC_MP_AHB4LPENSETR 0x858
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#define RCC_MP_AHB4LPENCLRR 0x85c
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#define RCC_MP_S_AHB4LPENSETR 0x868
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#define RCC_MP_S_AHB4LPENCLRR 0x86c
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#define RCC_MP_NS_AHB4LPENSETR 0x870
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#define RCC_MP_NS_AHB4LPENCLRR 0x874
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#define RCC_MP_AHB5LPENSETR 0x878
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#define RCC_MP_AHB5LPENCLRR 0x87c
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#define RCC_MP_AHB6LPENSETR 0x880
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#define RCC_MP_AHB6LPENCLRR 0x884
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#define RCC_MP_S_AHB6LPENSETR 0x888
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#define RCC_MP_S_AHB6LPENCLRR 0x88c
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#define RCC_MP_NS_AHB6LPENSETR 0x890
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#define RCC_MP_NS_AHB6LPENCLRR 0x894
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#define RCC_MP_S_AXIMLPENSETR 0x898
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#define RCC_MP_S_AXIMLPENCLRR 0x89c
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#define RCC_MP_NS_AXIMLPENSETR 0x8a0
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#define RCC_MP_NS_AXIMLPENCLRR 0x8a4
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#define RCC_MP_MLAHBLPENSETR 0x8a8
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#define RCC_MP_MLAHBLPENCLRR 0x8ac
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#define RCC_APB3SECSR 0x8c0
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#define RCC_APB4SECSR 0x8c4
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#define RCC_APB5SECSR 0x8c8
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#define RCC_APB6SECSR 0x8cc
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#define RCC_AHB2SECSR 0x8d0
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#define RCC_AHB4SECSR 0x8d4
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#define RCC_AHB5SECSR 0x8d8
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#define RCC_AHB6SECSR 0x8dc
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#define RCC_VERR 0xff4
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#define RCC_IDR 0xff8
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#define RCC_SIDR 0xffc
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/* RCC_SECCFGR register fields */
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#define RCC_SECCFGR_MCO1SECF 22
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#define RCC_SECCFGR_MCO2SECF 23
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/* RCC_APB3SECSR register fields */
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#define RCC_APB3SECSR_LPTIM2SECF 0
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#define RCC_APB3SECSR_LPTIM3SECF 1
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#define RCC_APB3SECSR_VREFSECF 13
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/* RCC_APB4SECSR register fields */
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#define RCC_APB4SECSR_DCMIPPSECF 1
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#define RCC_APB4SECSR_USBPHYSECF 16
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/* RCC_APB5SECSR register fields */
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#define RCC_APB5SECSR_RTCSECF 8
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#define RCC_APB5SECSR_TZCSECF 11
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#define RCC_APB5SECSR_ETZPCSECF 13
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#define RCC_APB5SECSR_IWDG1SECF 15
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#define RCC_APB5SECSR_BSECSECF 16
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#define RCC_APB5SECSR_STGENCSECF 20
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#define RCC_APB5SECSR_STGENROSECF 21
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/* RCC_APB6SECSR register fields */
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#define RCC_APB6SECSR_USART1SECF 0
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#define RCC_APB6SECSR_USART2SECF 1
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#define RCC_APB6SECSR_SPI4SECF 2
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#define RCC_APB6SECSR_SPI5SECF 3
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#define RCC_APB6SECSR_I2C3SECF 4
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#define RCC_APB6SECSR_I2C4SECF 5
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#define RCC_APB6SECSR_I2C5SECF 6
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#define RCC_APB6SECSR_TIM12SECF 7
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#define RCC_APB6SECSR_TIM13SECF 8
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#define RCC_APB6SECSR_TIM14SECF 9
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#define RCC_APB6SECSR_TIM15SECF 10
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#define RCC_APB6SECSR_TIM16SECF 11
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#define RCC_APB6SECSR_TIM17SECF 12
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/* RCC_AHB2SECSR register fields */
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#define RCC_AHB2SECSR_DMA3SECF 3
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#define RCC_AHB2SECSR_DMAMUX2SECF 4
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#define RCC_AHB2SECSR_ADC1SECF 5
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#define RCC_AHB2SECSR_ADC2SECF 6
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#define RCC_AHB2SECSR_USBOSECF 8
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/* RCC_AHB4SECSR register fields */
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#define RCC_AHB4SECSR_TSCSECF 15
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/* RCC_AHB5SECSR register fields */
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#define RCC_AHB5SECSR_PKASECF 2
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#define RCC_AHB5SECSR_SAESSECF 3
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#define RCC_AHB5SECSR_CRYP1SECF 4
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#define RCC_AHB5SECSR_HASH1SECF 5
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#define RCC_AHB5SECSR_RNG1SECF 6
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#define RCC_AHB5SECSR_BKPSRAMSECF 8
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/* RCC_AHB6SECSR register fields */
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#define RCC_AHB6SECSR_MCESECF 1
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#define RCC_AHB6SECSR_FMCSECF 12
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#define RCC_AHB6SECSR_QSPISECF 14
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#define RCC_AHB6SECSR_SDMMC1SECF 16
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#define RCC_AHB6SECSR_SDMMC2SECF 17
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#define RCC_AHB6SECSR_ETH1CKSECF 7
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#define RCC_AHB6SECSR_ETH1TXSECF 8
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#define RCC_AHB6SECSR_ETH1RXSECF 9
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#define RCC_AHB6SECSR_ETH1MACSECF 10
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#define RCC_AHB6SECSR_ETH1STPSECF 11
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#define RCC_AHB6SECSR_ETH2CKSECF 27
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#define RCC_AHB6SECSR_ETH2TXSECF 28
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#define RCC_AHB6SECSR_ETH2RXSECF 29
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#define RCC_AHB6SECSR_ETH2MACSECF 30
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#define RCC_AHB6SECSR_ETH2STPSECF 31
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/* Fields of RCC_BDCR register */
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#define RCC_BDCR_LSEON BIT(0)
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#define RCC_BDCR_LSEBYP BIT(1)
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#define RCC_BDCR_LSERDY BIT(2)
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#define RCC_BDCR_DIGBYP BIT(3)
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#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
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#define RCC_BDCR_LSEDRV_SHIFT 4
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#define RCC_BDCR_LSECSSON BIT(8)
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#define RCC_BDCR_RTCCKEN BIT(20)
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#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
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#define RCC_BDCR_RTCSRC_SHIFT 16
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/* Fields of RCC_RDLSICR register */
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#define RCC_RDLSICR_LSION BIT(0)
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#define RCC_RDLSICR_LSIRDY BIT(1)
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/* used for ALL PLLNCR registers */
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#define RCC_PLLNCR_PLLON BIT(0)
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#define RCC_PLLNCR_PLLRDY BIT(1)
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#define RCC_PLLNCR_SSCG_CTRL BIT(2)
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#define RCC_PLLNCR_DIVPEN BIT(4)
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#define RCC_PLLNCR_DIVQEN BIT(5)
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#define RCC_PLLNCR_DIVREN BIT(6)
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#define RCC_PLLNCR_DIVEN_SHIFT 4
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/* used for ALL PLLNCFGR1 registers */
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#define RCC_PLLNCFGR1_DIVM_SHIFT 16
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#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
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#define RCC_PLLNCFGR1_DIVN_SHIFT 0
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#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
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/* only for PLL3 and PLL4 */
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#define RCC_PLLNCFGR1_IFRGE_SHIFT 24
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#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
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/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
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#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
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#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
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#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
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#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
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#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
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#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
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#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
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#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
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/* used for ALL PLLNFRACR registers */
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#define RCC_PLLNFRACR_FRACV_SHIFT 3
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#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
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#define RCC_PLLNFRACR_FRACLE BIT(16)
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/* used for ALL PLLNCSGR registers */
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#define RCC_PLLNCSGR_INC_STEP_SHIFT 16
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#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
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#define RCC_PLLNCSGR_MOD_PER_SHIFT 0
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#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
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#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
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#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
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/* used for RCC_OCENSETR and RCC_OCENCLRR registers */
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#define RCC_OCENR_HSION BIT(0)
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#define RCC_OCENR_CSION BIT(4)
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#define RCC_OCENR_DIGBYP BIT(7)
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#define RCC_OCENR_HSEON BIT(8)
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#define RCC_OCENR_HSEBYP BIT(10)
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#define RCC_OCENR_HSECSSON BIT(11)
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/* Fields of RCC_OCRDYR register */
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#define RCC_OCRDYR_HSIRDY BIT(0)
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#define RCC_OCRDYR_HSIDIVRDY BIT(2)
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#define RCC_OCRDYR_CSIRDY BIT(4)
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#define RCC_OCRDYR_HSERDY BIT(8)
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/* Fields of DDRITFCR register */
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#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
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#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
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#define RCC_DDRITFCR_DDRCKMOD_SSR 0
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/* Fields of RCC_HSICFGR register */
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#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
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/* used for MCO related operations */
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#define RCC_MCOCFG_MCOON BIT(12)
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#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
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#define RCC_MCOCFG_MCODIV_SHIFT 4
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#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
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/* used for most of SELR register */
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#define RCC_SELR_SRC_MASK GENMASK(2, 0)
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#define RCC_SELR_SRCRDY BIT(31)
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/* used for most of DIVR register : max div for RTC */
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#define RCC_DIVR_DIV_MASK GENMASK(5, 0)
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#define RCC_DIVR_DIVRDY BIT(31)
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#endif /* STM32MP13_RCC_H */
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