64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2026 Renesas Electronics Corp.
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*
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* Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved.
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*/
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#ifndef __INCLUDE_DBSC5_H__
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#define __INCLUDE_DBSC5_H__
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/* The number of channels X5H has */
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#define DRAM_CH_CNT 16
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/* The number of slices X5H has */
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#define SLICE_CNT 2
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/* The number of chip select X5H has */
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#define CS_CNT 2
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struct renesas_dbsc5_board_config {
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u32 bdcfg_phyvalid;
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u32 bdcfg_tx_drv;
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u32 bdcfg_tx_ffc;
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u32 bdcfg_rx_odt;
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u8 bdcfg_rx_dfe;
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u8 bdcfg_tx_odt;
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u8 bdcfg_tx_ntodt;
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u8 bdcfg_tx_dfe;
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u8 bdcfg_rx_dca;
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u8 bdcfg_rx_drv;
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u32 bdcfg_rx_emphasis;
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u8 bdcfg_tx_dca;
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u8 bdcfg_ca_vref;
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u32 bdcfg_rx_vref;
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u32 bdcfg_rx_vref_step;
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u32 bdcfg_tx_vref;
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u8 bdcfg_rfm_chk;
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/* Board parameter about channels */
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struct {
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/*
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* 0x00: 4Gb dual channel die / 2Gb single channel die
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* 0x01: 6Gb dual channel die / 3Gb single channel die
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* 0x02: 8Gb dual channel die / 4Gb single channel die
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* 0x03: 12Gb dual channel die / 6Gb single channel die
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* 0x04: 16Gb dual channel die / 8Gb single channel die
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* 0x05: 24Gb dual channel die / 12Gb single channel die
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* 0x06: 32Gb dual channel die / 16Gb single channel die
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* 0x07: 24Gb single channel die
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* 0x08: 32Gb single channel die
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* 0xFF: NO_MEMORY
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*/
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u8 bdcfg_ddr_density[CS_CNT];
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/* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */
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u32 bdcfg_ca_swap;
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/* SoC dqsX([1][0]) -> MEM dqsY: */
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u8 bdcfg_dqs_swap;
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/* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */
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u32 bdcfg_dq_swap[SLICE_CNT];
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/* SoC dm -> MEM dqY/dm: (8 means DM) */
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u8 bdcfg_dm_swap[SLICE_CNT];
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} ch[DRAM_CH_CNT];
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};
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#endif /* __INCLUDE_DBSC5_H__ */
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