pmaports-rtwo/device/testing/linux-postmarketos-qcom-sm8550/panel-novatek-nt37705.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2026 snlavaise <snlavaise@gmail.com>
 *
 * DRM panel driver for the CSOT NT37705 (Novatek NT37705) command mode DSC
 * panel used on the Motorola rtwo (Moto Edge 40 Pro, SM8550).
 *
 * Sequences transcribed byte-by-byte from the vendor device tree node
 * "qcom,mdss_dsi_mot_csot_nt37705_667_curve_1080x2400_dsc_cmd_v1"
 * (panel name mipi_mot_cmd_csot_1080p_dsc_667, panel supplier "csot"),
 * see pmos/panel-nt37705-v1-dump.md. Only the 60 Hz timing (timing@0, 2f01 +
 * e000) is exposed for the first bring-up. The other rates only differ in
 * their timing-switch-command: 120 Hz 2f02/e041, 90 Hz 2f04/e000,
 * 48 Hz 2f05/e000, 165 Hz 2f03/e041 (same porches and DSI clock).
 *
 * DSC: besides the Novatek MCS setup in the on command (0x90 enable, 0x91
 * parameters), the standard PPS and compression-mode packets are sent after
 * it, same as the mainline NT37801 driver (same Novatek flow) and the
 * downstream driver, which sends the PPS by itself.
 */

#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/gpio/consumer.h>
#include <linux/ktime.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>

#include <video/mipi_display.h>

#include <drm/display/drm_dsc.h>
#include <drm/display/drm_dsc_helper.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_panel.h>
#include <drm/drm_probe_helper.h>

struct nt37705_csot {
	struct drm_panel panel;
	struct mipi_dsi_device *dsi;
	struct gpio_desc *reset_gpio;
	struct regulator_bulk_data *supplies;
	ktime_t off_since;
};

static const struct regulator_bulk_data nt37705_csot_supplies[] = {
	{ .supply = "vddio" },
	{ .supply = "vdd" },
	{ .supply = "vci" },
};

static inline struct nt37705_csot *to_nt37705_csot(struct drm_panel *panel)
{
	return container_of(panel, struct nt37705_csot, panel);
}

/*
 * Vendor reset-sequence: <0 12 1 1 0 1 1 13>  (value -> duration ms).
 * Those are raw line levels (downstream uses gpio_set_value()), while
 * reset-gpios is GPIO_ACTIVE_LOW here, so the logical values are inverted:
 * assert 12 ms, release 1 ms, assert 1 ms, release 13 ms (ends released).
 */
static void nt37705_csot_reset(struct nt37705_csot *ctx)
{
	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	usleep_range(12000, 13000);
	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	usleep_range(1000, 2000);
	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	usleep_range(1000, 2000);
	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
	usleep_range(13000, 14000);
}

/*
 * Rate control for DSC 1.1, 10 bpc, 8 bpp as the Motorola/Qualcomm downstream
 * driver sets it for panels flagged qcom,mdss-dsc-novateck-ic
 * (sde_dsc_populate_dsc_config_nt(), DSC_V11_10BPC_8BPP entry of the *_nt
 * tables). The DDIC decoder uses these fixed tables, which differ from the
 * generic VESA/drm ones in 8 of the 15 ranges, so the host encoder must use
 * them too; msm keeps a configuration filled in this completely (see
 * msm-dsi-keep-panel-dsc-config.patch). Derived values reproduce the stock
 * 0x91 bytes exactly.
 */
static const u8 nt37705_rc_min_qp[DSC_NUM_BUF_RANGES] = {
	0, 4, 5, 5, 7, 7, 7, 7, 7, 8, 9, 9, 9, 12, 16
};
static const u8 nt37705_rc_max_qp[DSC_NUM_BUF_RANGES] = {
	8, 8, 9, 10, 11, 11, 11, 12, 13, 14, 14, 15, 15, 16, 17
};
static const s8 nt37705_rc_bpg[DSC_NUM_BUF_RANGES] = {
	2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12
};
static const u8 nt37705_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
	0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
	0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
};

static void nt37705_csot_dsc_config_nt(struct drm_dsc_config *dsc)
{
	int bpp = dsc->bits_per_pixel >> 4;
	int bpc = dsc->bits_per_component;
	int groups_per_line, groups_total, slice_bits;
	int pre_mux_bits, mux_bits, final_scale, i;

	dsc->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
	dsc->first_line_bpg_offset = 13;
	dsc->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
	dsc->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST;
	dsc->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST;
	dsc->simple_422 = false;
	dsc->convert_rgb = true;
	dsc->vbr_enable = false;

	for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
		dsc->rc_buf_thresh[i] = nt37705_rc_buf_thresh[i];
	for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
		dsc->rc_range_params[i].range_min_qp = nt37705_rc_min_qp[i];
		dsc->rc_range_params[i].range_max_qp = nt37705_rc_max_qp[i];
		dsc->rc_range_params[i].range_bpg_offset =
			nt37705_rc_bpg[i] & DSC_RANGE_BPG_OFFSET_MASK;
	}

	dsc->rc_quant_incr_limit0 = 15;
	dsc->rc_quant_incr_limit1 = 15;
	dsc->initial_offset = 6144;
	dsc->initial_xmit_delay = 512;
	dsc->flatness_min_qp = 7;
	dsc->flatness_max_qp = 16;

	dsc->line_buf_depth = bpc + 1;
	dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;

	groups_per_line = DIV_ROUND_UP(dsc->slice_width, 3);
	dsc->slice_chunk_size = DIV_ROUND_UP(dsc->slice_width * bpp, 8);

	dsc->initial_dec_delay = DIV_ROUND_UP(dsc->rc_model_size -
					      dsc->initial_offset +
					      dsc->initial_xmit_delay * bpp +
					      groups_per_line *
					      dsc->first_line_bpg_offset, bpp) -
				 dsc->initial_xmit_delay;
	dsc->initial_scale_value = 8 * dsc->rc_model_size /
				   (dsc->rc_model_size - dsc->initial_offset);

	slice_bits = 8 * dsc->slice_chunk_size * dsc->slice_height;
	groups_total = groups_per_line * dsc->slice_height;

	dsc->nfl_bpg_offset = DIV_ROUND_UP(dsc->first_line_bpg_offset * 2048,
					   dsc->slice_height - 1);

	pre_mux_bits = 3 * (dsc->mux_word_size + (4 * bpc + 4) - 2);
	mux_bits = pre_mux_bits - (dsc->mux_word_size -
		   ((slice_bits - pre_mux_bits) % dsc->mux_word_size));

	dsc->slice_bpg_offset = DIV_ROUND_UP(2048 * (dsc->rc_model_size -
						     dsc->initial_offset +
						     mux_bits), groups_total);

	dsc->final_offset = dsc->rc_model_size -
			    dsc->initial_xmit_delay * bpp + mux_bits;
	final_scale = 8 * dsc->rc_model_size /
		      (dsc->rc_model_size - dsc->final_offset);
	dsc->scale_increment_interval = (2048 * dsc->final_offset) /
		((final_scale - 9) * (dsc->nfl_bpg_offset +
				      dsc->slice_bpg_offset));
	dsc->scale_decrement_interval = groups_per_line /
					(dsc->initial_scale_value - 8);
}

/*
 * Novatek 0x91: the panel-side DSC decoder parameters. The layout was checked
 * field by field against the mainline NT37801 driver, whose hardcoded 0x91
 * matches drm_dsc_compute_rc_parameters() exactly.
 *
 * Built from the config the host actually encodes with. With the Novatek
 * rate control above it yields exactly the stock bytes
 * (ab 28 00 0c d2 00 02 25 01 14 00 07 09 75 08 7a 10 f0).
 */
static void nt37705_csot_write_dsc_params(struct mipi_dsi_multi_context *dsi_ctx,
					  const struct drm_dsc_config *dsc)
{
	const u8 buf[] = {
		0x91,
		(dsc->bits_per_component << 4) | dsc->line_buf_depth,
		0x28,	/* stock value, same on NT37801 (block pred, 8 bpp) */
		dsc->slice_height >> 8, dsc->slice_height & 0xff,
		(dsc->first_line_bpg_offset << 4) | 0x2, 0x00,
		dsc->initial_dec_delay >> 8, dsc->initial_dec_delay & 0xff,
		dsc->scale_increment_interval >> 8,
		dsc->scale_increment_interval & 0xff,
		dsc->scale_decrement_interval >> 8,
		dsc->scale_decrement_interval & 0xff,
		dsc->nfl_bpg_offset >> 8, dsc->nfl_bpg_offset & 0xff,
		dsc->slice_bpg_offset >> 8, dsc->slice_bpg_offset & 0xff,
		dsc->final_offset >> 8, dsc->final_offset & 0xff,
	};

	mipi_dsi_dcs_write_buffer_multi(dsi_ctx, buf, sizeof(buf));
}

/*
 * Full 60 Hz on-command from timing@0 of the stock node, ending with
 * sleep-out (100 ms) and display-on as in the vendor sequence.
 */
static int nt37705_csot_on(struct nt37705_csot *ctx)
{
	struct mipi_dsi_device *dsi = ctx->dsi;
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };

	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba, 0x00, 0x6a, 0x00, 0x10, 0x09, 0xb0, 0x10);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x07);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba, 0x00, 0x6a, 0x00, 0x10, 0x00, 0x20, 0x10);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x0e);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xba, 0x00, 0x4c, 0x00, 0x10, 0x00, 0x2c, 0x10);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xbb, 0x00, 0x6a, 0x00, 0x10, 0x00, 0x20, 0x70);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc1, 0x00, 0x6a, 0x00, 0x6a, 0x00, 0x4c, 0x00, 0x6a, 0x00, 0x6a);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x41, 0x73, 0x73, 0x73, 0x83);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x00, 0x5c, 0xc4, 0xe8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0x10, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x41, 0x8d, 0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x07);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x37);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb7, 0x08, 0x08, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc0, 0x20);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xea, 0x22, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x21);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xea, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x83);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x03);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x08);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x81);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1e);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x0f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x05);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc5, 0x15, 0x15, 0x15);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x81);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x19);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfb, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x2d);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfc, 0x44);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x1a);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x55);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x83);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x12);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xfe, 0x41);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x18);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf4, 0x30);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x19);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf2, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xff, 0xaa, 0x55, 0xa5, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x31);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x01, 0x09);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x15);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf8, 0x01, 0x5e);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x10);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x00, 0x00, 0x04, 0x37);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x00, 0x00, 0x09, 0x5f);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x80);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x04);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x20);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x90, 0x03, 0x03);
	nt37705_csot_write_dsc_params(&dsi_ctx, dsi->dsc);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x01);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xc7, 0x00, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x40);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xf0, 0x55, 0xaa, 0x52, 0x08, 0x00);
	mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x01, 0x60);
	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
	mipi_dsi_msleep(&dsi_ctx, 100);
	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);

	return dsi_ctx.accum_err;
}

/*
 * Bring-up aid: the stock ESD check reads DCS 0x0a and expects 0x9c (booster
 * on, sleep out, display on, normal mode). Logs the result either way.
 */
static void nt37705_csot_log_power_mode(struct nt37705_csot *ctx,
					const char *when)
{
	struct device *dev = &ctx->dsi->dev;
	u8 power_mode;
	int ret;

	ret = mipi_dsi_dcs_get_power_mode(ctx->dsi, &power_mode);
	if (ret < 0)
		dev_warn(dev, "power mode %s: read failed: %d\n", when, ret);
	else
		dev_info(dev, "power mode %s: 0x%02x (stock expects 0x9c)\n",
			 when, power_mode);
}

static int nt37705_csot_off(struct nt37705_csot *ctx)
{
	struct mipi_dsi_device *dsi = ctx->dsi;
	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };

	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
	mipi_dsi_msleep(&dsi_ctx, 120);

	return dsi_ctx.accum_err;
}

/*
 * Everything is sent from prepare (DSI host already up thanks to
 * prepare_prev_first), followed by the standard PPS and compression-mode
 * packets, like the mainline NT37801 driver does with the same Novatek
 * 0x90/0x91 flow. The downstream Qualcomm driver also sends the PPS on its
 * own; it is not part of the vendor on-command.
 */
static int nt37705_csot_prepare(struct drm_panel *panel)
{
	struct nt37705_csot *ctx = to_nt37705_csot(panel);
	struct device *dev = &ctx->dsi->dev;
	struct drm_dsc_picture_parameter_set pps;
	s64 elapsed;
	int ret;

	/* Supplies were cut in probe or unprepare: keep them off >= 100 ms. */
	elapsed = ktime_ms_delta(ktime_get(), ctx->off_since);
	if (elapsed < 100)
		msleep(100 - elapsed);

	ret = regulator_bulk_enable(ARRAY_SIZE(nt37705_csot_supplies), ctx->supplies);
	if (ret < 0)
		return ret;

	nt37705_csot_reset(ctx);

	ret = nt37705_csot_on(ctx);
	if (ret < 0) {
		dev_err(dev, "failed to initialize panel: %d\n", ret);
		goto err;
	}

	drm_dsc_pps_payload_pack(&pps, ctx->dsi->dsc);

	ret = mipi_dsi_picture_parameter_set(ctx->dsi, &pps);
	if (ret < 0) {
		dev_err(dev, "failed to transmit PPS: %d\n", ret);
		goto err;
	}

	ret = mipi_dsi_compression_mode(ctx->dsi, true);
	if (ret < 0) {
		dev_err(dev, "failed to enable compression mode: %d\n", ret);
		goto err;
	}

	msleep(28);

	nt37705_csot_log_power_mode(ctx, "after on");
	msleep(100);
	nt37705_csot_log_power_mode(ctx, "after on +100ms");
	msleep(400);
	nt37705_csot_log_power_mode(ctx, "after on +500ms");

	return 0;

err:
	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	regulator_bulk_disable(ARRAY_SIZE(nt37705_csot_supplies), ctx->supplies);
	ctx->off_since = ktime_get();

	return ret;
}

static int nt37705_csot_unprepare(struct drm_panel *panel)
{
	struct nt37705_csot *ctx = to_nt37705_csot(panel);
	struct device *dev = &ctx->dsi->dev;
	int ret;

	ret = nt37705_csot_off(ctx);
	if (ret < 0)
		dev_err(dev, "failed to un-initialize panel: %d\n", ret);

	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
	regulator_bulk_disable(ARRAY_SIZE(nt37705_csot_supplies), ctx->supplies);
	ctx->off_since = ktime_get();

	return 0;
}

/*
 * 60 Hz modeline, geometry from the stock timing@0:
 * hbp/hfp/hpw = 0x20/0x20/0x10, vbp/vfp/vpw = 0x04/0x0c/0x04 (1080x2400).
 */
static const struct drm_display_mode nt37705_csot_mode = {
	.clock = (1080 + 32 + 16 + 32) * (2400 + 4 + 12 + 4) * 60 / 1000,
	.hdisplay = 1080,
	.hsync_start = 1080 + 32,
	.hsync_end = 1080 + 32 + 16,
	.htotal = 1080 + 32 + 16 + 32,
	.vdisplay = 2400,
	.vsync_start = 2400 + 4,
	.vsync_end = 2400 + 4 + 12,
	.vtotal = 2400 + 4 + 12 + 4,
	.width_mm = 69,
	.height_mm = 154,
	.type = DRM_MODE_TYPE_DRIVER,
};

static int nt37705_csot_get_modes(struct drm_panel *panel,
				  struct drm_connector *connector)
{
	return drm_connector_helper_get_modes_fixed(connector, &nt37705_csot_mode);
}

static const struct drm_panel_funcs nt37705_csot_panel_funcs = {
	.prepare = nt37705_csot_prepare,
	.unprepare = nt37705_csot_unprepare,
	.get_modes = nt37705_csot_get_modes,
};

/*
 * DBV (0x51) backlight, 12-bit (0..0x3ffc on the stock panel). The vendor
 * "bl-is-exponent"/"bl-inverted-dbv" curves are not reproduced; a raw value
 * is written for now so the display has a working brightness control.
 */
static int nt37705_csot_bl_update_status(struct backlight_device *bl)
{
	struct mipi_dsi_device *dsi = bl_get_data(bl);
	u16 brightness = backlight_get_brightness(bl);

	return mipi_dsi_dcs_set_display_brightness_large(dsi, brightness);
}

static int nt37705_csot_bl_get_brightness(struct backlight_device *bl)
{
	struct mipi_dsi_device *dsi = bl_get_data(bl);
	u16 brightness;
	int ret;

	ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness);
	if (ret < 0)
		return ret;

	return brightness;
}

static const struct backlight_ops nt37705_csot_bl_ops = {
	.update_status = nt37705_csot_bl_update_status,
	.get_brightness = nt37705_csot_bl_get_brightness,
};

static struct backlight_device *
nt37705_csot_create_backlight(struct mipi_dsi_device *dsi)
{
	struct device *dev = &dsi->dev;
	const struct backlight_properties props = {
		.type = BACKLIGHT_RAW,
		.brightness = 2047,
		.max_brightness = 16380,
	};

	return devm_backlight_device_register(dev, dev_name(dev), dev, dsi,
					      &nt37705_csot_bl_ops, &props);
}

static int nt37705_csot_probe(struct mipi_dsi_device *dsi)
{
	struct device *dev = &dsi->dev;
	struct nt37705_csot *ctx;
	struct drm_dsc_config *dsc;
	int ret;

	ctx = devm_drm_panel_alloc(dev, struct nt37705_csot, panel,
				   &nt37705_csot_panel_funcs,
				   DRM_MODE_CONNECTOR_DSI);
	if (IS_ERR(ctx))
		return PTR_ERR(ctx);

	ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(nt37705_csot_supplies),
					    nt37705_csot_supplies, &ctx->supplies);
	if (ret < 0)
		return dev_err_probe(dev, ret, "Failed to get regulators\n");

	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
	if (IS_ERR(ctx->reset_gpio))
		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio),
				     "Failed to get reset-gpios\n");

	/*
	 * The ABL leaves the panel powered and running its splash. Resetting
	 * it, or even power-cycling it from prepare (DSI PHY already up, lanes
	 * in LP11), leaves the DDIC dead: no TE, no DCS read response. The same
	 * power cycle done with the DSI link down (fb blank/unblank) brings it
	 * up fine every time, so cut the inherited supplies here, while MDSS
	 * has just been reset and the DSI PHY is still off.
	 */
	ret = regulator_bulk_enable(ARRAY_SIZE(nt37705_csot_supplies),
				    ctx->supplies);
	if (ret < 0)
		return dev_err_probe(dev, ret, "Failed to enable regulators\n");
	regulator_bulk_disable(ARRAY_SIZE(nt37705_csot_supplies), ctx->supplies);
	ctx->off_since = ktime_get();

	/* Stock DSC config: version 1.1, 10 bpc, 8 bpp, novateck-ic flow. */
	dsc = devm_kzalloc(dev, sizeof(*dsc), GFP_KERNEL);
	if (!dsc)
		return -ENOMEM;

	dsc->pic_width = 1080;
	dsc->pic_height = 2400;
	dsc->dsc_version_major = 0x1;
	dsc->dsc_version_minor = 0x1;
	dsc->slice_height = 12;
	dsc->slice_width = 540;
	dsc->slice_count = 2;
	dsc->bits_per_component = 10;
	dsc->bits_per_pixel = 8 << 4;
	dsc->block_pred_enable = true;
	nt37705_csot_dsc_config_nt(dsc);

	dsi->dsc = dsc;

	ctx->dsi = dsi;
	mipi_dsi_set_drvdata(dsi, ctx);

	dsi->lanes = 4;
	dsi->format = MIPI_DSI_FMT_RGB888;
	dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM;

	ctx->panel.prepare_prev_first = true;

	ctx->panel.backlight = nt37705_csot_create_backlight(dsi);
	if (IS_ERR(ctx->panel.backlight))
		return dev_err_probe(dev, PTR_ERR(ctx->panel.backlight),
				     "Failed to create backlight\n");

	drm_panel_add(&ctx->panel);

	ret = devm_mipi_dsi_attach(dev, dsi);
	if (ret < 0) {
		drm_panel_remove(&ctx->panel);
		return dev_err_probe(dev, ret, "Failed to attach to DSI host\n");
	}

	return 0;
}

static void nt37705_csot_remove(struct mipi_dsi_device *dsi)
{
	struct nt37705_csot *ctx = mipi_dsi_get_drvdata(dsi);

	drm_panel_remove(&ctx->panel);
}

static const struct of_device_id nt37705_csot_of_match[] = {
	{ .compatible = "novatek,nt37705" },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, nt37705_csot_of_match);

static struct mipi_dsi_driver nt37705_csot_driver = {
	.probe = nt37705_csot_probe,
	.remove = nt37705_csot_remove,
	.driver = {
		.name = "panel-novatek-nt37705",
		.of_match_table = nt37705_csot_of_match,
	},
};
module_mipi_dsi_driver(nt37705_csot_driver);

MODULE_AUTHOR("snlavaise <snlavaise@gmail.com>");
MODULE_DESCRIPTION("DRM driver for the CSOT NT37705 (Novatek) cmd mode DSC panel on Motorola rtwo");
MODULE_LICENSE("GPL");